RM0319 datasheet(87/368 Pages) STMICROELECTRONICS

87 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

87/368

Partial array self-refresh

For mobile applications, the memory controller is able to support refresh operations to

subsections of the memory array. To simplify this duty, separate parameters are provided to

supply the EMRS data for each chip select. These are the emrs_data_X parameters, where

X represents the chip select.

Having separate control parameters for the EMRS data allows the individual chips to set

their own masked refresh. The write_modereg parameter controls the writing of this EMRS

data into the registers. When write_modereg is set to 1'b1 initially, the EMRS register of chip

select 0 will be written. Each subsequent setting of the write_modereg parameter to 1'b1 will

write the EMRS register of the next chip select (1, 2, then 3).

Note:

The memory controller does not check if operations attempt to access addresses outside

the refresh ranges set by the EMRS registers, so any access to these addresses may result

in corrupt or lost data.

6.4.6

Out-of-range address checking

It is possible that the master attempts to write to an invalid address. For this reason, all

incoming addresses are always checked against the addressable physical memory space. If

a transaction is addressed to an out-of-range memory location, bit 0 of the int_status

parameter will be set to 1'b1 to alert the user of this condition. The memory controller will

record the address, source ID, length and type of transaction that caused the out-of-range

interrupt in the out_of_range_addr, out_of_range_source_id, out_of_range_length and

out_of_range_type parameters.

Reading the out-of-range parameters will trigger the memory controller to empty these

parameters and allow them to store out-of-range access information for future errors. The

interrupt should be acknowledged by setting bit 0 of the int_ack parameter to 1'b1, which will

in turn cause bit 0 of the int_status parameter to be cleared to 1'b0.

If a second out-of-range access occurs before the first out-of-range interrupt is

acknowledged, bit 1 of the int_status parameter will be set to 1'b1 to indicate that multiple

out-of-range accesses have occurred. If the out-of-range parameters have been read when

the second out-of-range error occurs, the details for this transaction will be stored in the out-

of-range parameters. If they have not been read, the details of the second error will be lost.

Even though the address has been identified as erroneous, the memory controller will still

process the READ or WRITE transaction. A READ transaction will return random data

which the user must receive to avoid stalling the memory controller. A WRITE transaction

will write the associated data to an unknown location in the memory array, potentially over-

writing other stored data. The command can not be aborted once accepted into the memory

controller.

6.4.7

Mobile devices DQS

For Mobile applications the user must add pull-down resistors on the DRAM boundary to the

DQS and DQS_n pins. These resistors enable the system to open the gate early without

receiving bad data. Both the resistors are very important and the system can not function

accurately without them.

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