RM0319 datasheet(97/368 Pages) STMICROELECTRONICS

97 / 368 page

RM0319

Serial NOR Flash controller (SMI)

Doc ID 022640 Rev 3

97/368

7.3.4

Data transfers

Read request

A read request from an AHB master to external SPI memory is served only if SMI is in

hardware mode, and write burst mode is not enabled. Otherwise, an error flag is set (ERF1

flag in the SMI_SR register, and an ERROR response is sent back to the AHB master.

When a read request occurs in normal mode (that is, frequency up to 20 MHz), the SMI

sends the following data sequence to the bank selected by the AHB address bits [24.25].

●

Read data bytes instruction opcode (8’h03)

●

3- or 2-byte address (depending on the ADD_LENGTH bit of SMI_CR1 register, from

the MSB to the LSB,

●

Then, clock is sent to the memory until the end of burst requested by the AHB master.

In contrast, when a read request occurs in fast mode (that is, frequency ranging from

20 MHz to 50 MHz), the following sequence is sent:

●

Read data bytes at high speed instruction opcode (8’h0B),

●

3- or 2-byte address (depending on the ADD_LENGTH bit of SMI_CR1 register, from

the MSB to the LSB,

●

1 dummy byte (8’h00),

●

The clock is sent to the memory until the end of burst requested by the AHB master.

The external memory bank remains selected as long as

●

There is no external memory address jump,

●

No new commands are sent to the SMI (such as write enable request, read status

prescaler configuration change),

●

No memory access error occurs.

Note:

The memory bank also remains selected when the address rolls over from 0x00FF_FFFF to

0x0000.0000 within the same bank.

Write request

A write request from the AHB master to external SPI memory is served only if SMI is in

hardware mode, otherwise an error flag is set (ERF1 flag in the SMI_SR register). Wrapping

bursts is not allowed as long as external SPI memories do not support them, and an

ERROR response is sent back to the AHB master.

When a write request occurs, this request is forwarded to external memory only if both

following conditions are fulfilled:

●

First, the selected bank should be in write mode (the corresponding bit in WM field of

SMI_SR register is flagged). Otherwise, a dedicated error flag is set (the ERF2 flag in

the SMI_SR register) and an ERROR response is sent back to the AHB master.

Note:

To enable write mode, select the memory bank using the BS bits in the SMI_CR2 register,

and then set the WEN bit in the SMI_CR1 register.

●

Second, no write should be in progress. The WIP bit of external memory status register

in the SMI_SR register (bit [0]) must be cleared. If this condition is not met, AHB is

stalled until WIP = 1‘b0.

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