RM0319 datasheet(89/368 Pages) STMICROELECTRONICS

89 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

89/368

in the internal memory controller registers are programmed (Section 6.5). The exact number

and values of these parameters depends on the configuration and the type of memory for

which the memory controller was designed.

The mapping of the address space to the internal data storage structure of the DRAM

devices is based on the actual size of the DRAM devices available. The size is stored in

user-programmable parameters that must be initialized at power up. Certain DRAM devices

allow for different mapping options to be chosen, while other DRAM devices depend on the

burst length chosen.

DDR SDRAM address mapping options

The address structure of DDR SDRAM devices contains five fields. Each of these fields can

be individually addressed when accessing the DRAM. The address map for this memory

controller is ordered as follows:

“Chip Select - Row - Bank - Column - Datapath”

The maximum widths of the fields are based on the configuration settings. The actual widths

of the fields may be smaller if the device address width parameters (addr_pins,

eight_bank_mode and column_size) are programmed differently.

Maximum address space

The maximum user address range is determined by the width of the memory datapath, the

number of chip select pins, and the address space of the DRAM device. The maximum

amount of memory can be calculated by the following formula:

Max Memory Bytes = ChipSelects x 2Address x NumBanks x DPWidthBytes

For this memory controller, the maximum values for these fields are as follows:

●

Chip Selects = 2

●

Device Address = 15+14 (Row+Column)

●

Number of Banks = 8

●

Datapath Width in Bytes = 2 bytes

As a result, the maximum addressable memory area is 16 GB. The maximum memory

capacity is 1GB, which can be implemented with different combinations of these

parameters.

Memory mapping to address space

The maximum allowable address space and mapping into the DRAM devices for the

memory controller is shown in Figure 19. This map corresponds to a memory device with 15

row bits and 14 column bits.

Figure 19.

Memory map: Maximum

The addr_pins and column_size parameters can range from the maximum configured for

the memory controller to seven bits smaller than the maximum configured. This allows the

memory controller to work with a wide variety of memory device sizes.

Chip Select

Row

Bank

Column

Data Path

33 32

18 17

15 14

1 0

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