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RM0319 数据表(PDF) 76 Page - STMicroelectronics |
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RM0319 数据表(HTML) 76 Page - STMicroelectronics |
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76 / 368 page ![]() Multiport DDR controller (MPMC) RM0319 76/368 Doc ID 022640 Rev 3 Priority relaxing allows low priority commands to be able to move through the arbiter to the core. This will ensure that the system can meet maximum latency requirements. Port pairing The memory controller arbiter embeds a feature which allows adjacent ports to be grouped together and considered jointly for arbitration. The weighted_round_robin_weight_sharing parameter controls this function, with one bit per pair of ports in the memory controller. Bit 0 handles ports 0 and 1, Bit 1 handles ports 2 and 3 and so on. Where memory controller interfaces to an odd number of ports, the highest numbered port is excluded from the port pairing system. Since the ports are grouped together, their relative priorities are not considered separately. Referring to Section , the general formula for port priority allocation is the ratio of that port's relative priority (ahbX_priorityY_relative_priority) to the sum of all requesting port's relative priority values. In this case, the relative priority value of only one of the paired ports is used for the sum calculation. This means that the bandwidth will be divided differently among the ports. Let us consider the port pair at the top of the scan order: if one only port is requesting it will win arbitration. If both are requesting, port ordering is used to determine which port wins arbitration. When the ports are paired, their scan order can never be altered and they will always remain together in the scan order. Their counters increment together, so when they reach their relative priority value, the port pair will dynamically be placed at the bottom of the scan order for that priority group. In order for port weight sharing to be used, the relative priority parameters for the port pair must be programmed to the same value and the port order of the paired ports should be sequential. If either condition is not followed, an error bit will be set to1'b1. Let us consider System G as described inTable 28. Again, to simplify the command queue is considered to never be full, commands from ports 0, 1, 2 and 3 are only received at priority level 0 and commands from ports 4 and 5 are always at priority 1. However, now ports P0 - P1, and ports P4 - P5 are paired. 6 Y Y P0 P0 110 010 P0-P1-P3-P2 P4-P5 7 Y Y Y P4 P4 110 020 P0-P1-P3-P2 P5-P4 8 Y Y Y Y P0 210 000 P0-P1-P3-P2 P5-P4 9 Y Y Y Y P1 220 000 P0-P1-P3-P2 P5-P4 10 Y Y Y Y P2 P2 221 000 P0-P1-P3-P2 P5-P4 Table 27. System F operation with priority relaxing (continued) Cycle Ports Requesting Relaxed Ports Arbitration Winner Next Counter Next Scan Order P 0 P 1 P 2 P 3 P 4 P 5 P 0 P 1 P 2 P 3 P 4 P 5 |
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