RM0319 datasheet(95/368 Pages) STMICROELECTRONICS

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RM0319

Serial NOR Flash controller (SMI)

Doc ID 022640 Rev 3

95/368

AHB-to-SMI interface

Acting as an AHB slave interface, the SMI is accessed by the AHB master through the AHB

bus. The following rules apply to this interface:

●

Endianness is fixed to little-endian.

●

SPLIT / RETRY responses from AHB slave (that is., the SMI) are not supported.

●

Size of data transfers to external serial memories can be byte, half-word or word (8-/16-

or 32-bit).

●

Size of data transfers to SMI registers must be 32 bits.

●

Read requests: all types of BURST defined by AHB protocol are supported (single,

wrapping and incrementing). Please note that wrapping bursts take more time than

incrementing bursts, because there is a break in the address increment.

Note:

If EEPROMs are used instead of Flash memories, the read request address should be

(ADDRESS + 1), where ADDRESS should be the actual target address to be read.

●

Write requests: wrapping bursts are not supported, causing an ERROR response on

HRESP sent back by SMI to AHB master.

●

Bursts must not cross bank boundaries.

●

In case of BUSY transfers, the SMI is held until BUSY is inactive.

SMI-to-MEMORY interface

Acting as a SPI master, the SMI supports a synchronous full-duplex data link with its up to 2

SPI slaves (the serial memory devices).

Each SPI slave must agree with the communication protocol fixed by SMI in terms of clock

polarity (CPOL) and clock phase (CPHA), specifically CPOL = 1 and CPHA = 1 (where clock

idles high and data is shifted in and out on the rising edge of the clock).

Prior to any operation involving a SPI-compatible off-chip memory device, the related SPI

slave must be selected by SMI (through chip select), then an 1-byte instruction must be sent

by SMI to the selected memory. The set of instructions supported by SMI is given in

Table 34.

7.3.3

Operation modes

SMI can run in two operation modes:

●

Hardware mode, by clearing the SW bit in the SMI_CR1 register.

●

Software mode, by setting the SW bit in the SMI_CR1 register.

Table 34.

SMI supported instruction

Opcode

Description

8’h03

Read data bytes.

8’h0B

Read data bytes at high speed.

8’h05

Read status register.

8’h06

Write enable.

8’h02

Page program.

8’hAB

Release from deep power-down.

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