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RM0319 数据表(PDF) 34 Page - STMicroelectronics |
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RM0319 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 368 page ![]() Multilayer interconnect matrix (BUSMATRIX) RM0319 34/368 Doc ID 022640 Rev 3 In the miscellaneous register bank, eight registers are allocated (ICM_x_ARB_CFG), one for each ICM. These registers have all the same layout: ● The 31st bit is in charge of choosing the arbitration scheme: fixed priority or round robin ● Bits [30:28] specify the priority starting level in case of round robin arbitration protocol ● Then 3 bits are allocated to each layer to set the priority level in case of fixed priority scheme: bits [2:0] for Layer0, [5:3] for Layer1 and so on. 3 Sbs_Basic 4 Sbs_Highspeed 5 MemCtr#2 (MPMC) 6Ras_F 7 MemCtr#3 (MPMC) 8 MemCtr#4 (MPMC) Table 6. ICM slaves (targets) (continued) ICM M1 |
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