RM0319 datasheet(85/368 Pages) STMICROELECTRONICS

85 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

85/368

When a lowpower_control parameter bit is set to 1'b1 by the user, the memory controller

checks the lowpower_auto_enable parameter.

●

If the associated bit in the lowpower_auto_enable parameter is set to 1'b1, the memory

controller will watch the associated counter for expiration and then enter that low power

mode.

●

Table 31 shows the correlation between the low power modes and the counters that

control each mode's automatic entry.

●

If the associated bit in the lowpower_auto_enable parameter is cleared to 1'b0, the

memory controller will complete its current memory burst access and then enter the

specified low power mode.

Note:

The values in lowpower_auto_enable parameter are only relevant when the associated

lowpower_control bit is set to 1'b1.

Multiple bits of the lowpower_control and lowpower_auto_enable parameters can be set to

1'b1 at the same time. When this happens, the memory controller always enters the deepest

low power mode of all the modes that are enabled.

If the memory controller is already in one low power mode when a deeper low power mode

is automatically or manually requested, first it exits the current low power mode and then

enters the deeper low power mode. A minimum 15 cycle delay occurs before the second

entry occurs.

The timing for automatic entry into any of the low power modes is based on the number of

idle cycles that have elapsed in the memory controller. There are 4 counters related to the 5

low power modes to determine when any particular low power mode will be entered if the

Memory Self-Refresh (Mode 3)

lowpower_control [2] =1'b1

lowpower_auto_enable [2]:

1'b0 = Manual

1'b1 = Automatic

Memory Self-Refresh with Memory Clock

Gating (Mode 4)

lowpower_control [1] =1'b1

lowpower_auto_enable [1]:

1'b0 = Manual

1'b1 = Automatic

Memory Self-Refresh with Memory and

Controller Clock Gating (Mode 5)

lowpower_control [0] =1'b1

lowpower_auto_enable [0]:

1'b0 = Manual

1'b1 = Automatic

Table 31.

Low power mode controls

Low Power Mode

Counter

Memory Power-Down (Mode 1)

lowpower_power_down_cnt

Memory Power-Down with Memory Clock Gating (Mode 2)

lowpower_power_down_cnt

Memory Self-Refresh (Mode 3)

lowpower_self_refresh_cnt

Memory Self-Refresh with Memory Clock Gating (Mode 4)

lowpower_external_cnt

Memory Self-Refresh with Memory and Controller Clock Gating

(Mode 5)

lowpower_internal_cnt

Table 30.

Low power mode parameters (continued)

Low Power Mode

Enable

Entry

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