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RM0319 数据表(PDF) 31 Page - STMicroelectronics |
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RM0319 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 368 page  RM0319 Multilayer interconnect matrix (BUSMATRIX) Doc ID 022640 Rev 3 31/368 Figure 3. SPEAr320S block diagram with BUSMATRIX topology details The switch matrix structure allows different subsystem dataflows to be executed in parallel improving the core platform efficiency. High performance master agents are directly interconnected with the memory controller reducing the memory access latency. Three different memory paths (two of them shared with other masters) are reserved for the programmable logic to enhance the user application throughput. The overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round-robin arbitration mechanism. Table 3 shows the connectivity matrix. Multilayer AHB interconnect matrix Multiport memory controller DDR memory interface JTAG/ETM9 Reconfigurable array subsystem ARM926EJS GPIO Int.Ctrl Timer QP RI-O M0 cfg 102 56 0/18 MII to PHY Oscillator 0÷6 0÷7 0÷2 0÷2 98 GPIO, 4clk Master reset 10 Low speed subsystem Basic subsystem 2 5 2 1 0÷6 C I Debug 12 8 chan. Master clock 0÷8 DDR 3-12 4 3 SPEAr320S 16KB Instr Cache 16KB Data Cache System controller Timer RTC GPIO SMI CPU subsystem 8KB SRAM JPEG Codec IrDA I2C0 SSP0 UART0 ADC 74.5 KB RAM Cuts: Half Dual Port (AHB wired): 2048 *32 *1 Dual Port: 96 *128 *1 1024 *32 *4 128 *8 *8 Single Port: 2048 *32 *2 1024 *32 *2 512 *32 *4 2048 *8 *8 Application subsystem C3 USB 2.0 Host USB 2.0 Device Ethernet MAC High speed subsystem 8-channel DMA 32KB ROM MISC Watchdog timer SDIO MII CLCD FSMC/ EMI SSP1/2 SPP UART1 to UART6 PWM CAN0/1 Touch- screen I2C1/2 M H G F E L D B A 3 4 1 5 7 6 2 5-23 9-4 10-6 4-12 2-12(4) 6-67 7-34 8-5 1-123 M2 M1 M3 M4 RMII0/1 I2S RS485 CLCD |
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