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RM0319 数据表(PDF) 73 Page - STMicroelectronics

部件名 RM0319
功能描述  SPEAr320S architecture and functionality
PDF  368 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

RM0319 数据表(HTML) 73 Page - STMicroelectronics

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RM0319
Multiport DDR controller (MPMC)
Doc ID 022640 Rev 3
73/368
If the same system also contains two ports that only can request at priority level 1, the
system behavior will be slightly altered. Adding these 2 ports leads to the second priority
group structure increasing the arbitration depth. Table 24 describes this system. The text in
bold-italic (grey background) highlights the priority level changes for P4 and P5.
To simplify, the command queue is again considered to never be full and it is assumed that
commands from ports 0, 1, 2 and 3 are only received at priority level 0. The behavior is
shown in Table 25.
Note:
If any priority 0 port (P0, P1, P2, P3) is requesting, the system will behave as one only
priority group is acting as shown in Table 23. Ports 4 and 5 can only win arbitration when no
higher-priority commands exist.
Table 23.
System D operation
Cycle
Ports requesting
Arbitration
winner
Next counter
Next scan order
P0
P1
P2
P3
P0
P1
P2
P3
P0-P1-P2-P3
0
Y
Y
Y
P0
100
0P0-P1-P2-P3
1
Y
Y
Y
P0
200
0P0-P1-P2-P3
2
Y
YYYP0
3
0
0
0
P0-P1-P2-P3
3
Y
YYYP0
4
0
0
0
P1-P2-P3-P0
4
Y
YYYP1
0
1
0
0
P1-P2-P3-P0
5
Y
YYYP1
0
2
0
0
P1-P2-P3-P0
6
Y
YYYP1
0
3
0
0
P2-P3-P0-P1
7
Y
Y
Y
P2
001
0P2-P3-P0-P1
8
Y
Y
Y
P2
002
0P3-P0-P1-P2
9
Y
Y
P3
000
1P0-P1-P2-P3
10
Y
Y
Y
P0
100
0P0-P1-P2-P3
11
Y
Y
P2
101
0P0-P1-P2-P3
12
Y
Y
P2
102
0P0-P1-P3-P2
Table 24.
System E specifications
Parameter
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
ahbX_priority0_relative_priority
4
3
2
1
1
1
ahbX_priority1_relative_priority
1
1
1
1
3
2
ahbX_port_ordering
0
1
2
3
4
5



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