RM0319 datasheet(67/368 Pages) STMICROELECTRONICS

67 / 368 page

RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

67/368

There are a fixed number of latency cycles in the memory controller, based on the pipeline

through the memory controller logic. These steps are:

●

Command passing through the port interface. (fixed)

●

Arbitration through the arbiter. (fixed)

●

Placement into the Command Queue. (fixed)

●

Memory Command Generation. (variable)

●

Sending of control signals from the core logic to flip-flops near the I/O drivers. (fixed)

●

Flight time to the DRAM device. (variable)

●

Flight time from the DRAM device. (variable)

●

For READs, synchronization of READ data from the data strobe domain. (fixed)

●

For READs, data pass through the port interface. (fixed)

For asynchronous AHB interfaces, additional 4-5 cycles are included for the round-trip

transaction to synchronize to the Database core clock. Some typical scenarios for a

multiport AHB interface and their effects on latency are:

●

Read latency with a page hit and empty queue.

●

(9) + Cas Latency

●

Read latency with a page miss to a closed page and an empty queue.

●

Trcd + Cas latency + (9)

●

Read latency with a page miss to an open page and an empty queue.

●

Trp+Trcd+Cas latency+9

●

Read latency with a page hit and a currently executing transaction.

●

TBurst end+Cas Latency+9

●

Read latency with a page miss to a closed bank and a currently executing transaction.

The page open command will be executed while the current burst is completing if

possible.

●

MAX(Trcd, TBurst end)+ Cas Latency + 9

●

Read latency with a page miss to an open page and an empty queue. The page close

command will be executed while the current burst is completing if possible.

●

MAX(Trp+Trcd,TBurst end)+Cas latency+9

TBurst end equals the time to complete the current burst in progress. The maximum value

here is 3 for a READ command and 3 + twr for a WRITE command if the burst count is

configured to 8 for DDR DRAM devices. The minimum value is 0.

6.3.8

Multiport arbiter

The arbiter manages arbitrating requests from the ports and sending requests to the core.

Each transaction received by the arbiter logic has an associated priority, which works with

each port's arbitration logic to determine how ports issue requests to the core. The MPMC

supports the weighted round-robin arbitration scheme.

The arbiter logic routes READ data from the core to the appropriate port. The requesting

port is assumed to be able to receive the data. WRITE data from each port is connected

directly to its own WRITE data interface inside the core, allowing the ports to independently

pass them to the core buffers.

Arbitration overview

RM0319 数据表(PDF) 67 Page - STMicroelectronics

RM0319 数据表(HTML) 67 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载