RM0319 datasheet(90/368 Pages) STMICROELECTRONICS

90 / 368 page

Multiport DDR controller (MPMC)

RM0319

90/368

Doc ID 022640 Rev 3

The settings for the addr_pins and column_size parameters control how the address map is

used to decode the user address to the DRAM chip selects and row and column addresses.

The eight_bank_mode parameters control the address in DDR2 mode. It is assumed that

the values in these parameters never exceed the maximum values configured.

Using the example shown in Figure 19, if the memory controller is wired to devices with 12

row pins and 12 column bits, the maximum accessible memory space would be reduced.

The accessible memory space for this configuration is 512 MB.

The address map for this configuration is shown in Figure 20.

Note:

Address bits 29 through 33 are not used. These bits are ignored when generating the

address to the DRAM devices

Figure 20.

Alternate memory map

Note:

The Chip Select, Row, Bank, and Column fields are used to address an entire memory

word, and the Datapath bits are used to address individual bytes within that user word. For

example, for a read starting at byte address 0x2, the Datapath bits must be defined as

3'b010 in order to address this byte directly. READs and WRITEs are memory word-aligned

if all the Datapath bits are 0.

6.4.11

DCC tuning timing

The command and address for the transaction are sent from the memory controller

coincident with the falling edge of the memory controller clock. Since the clock, command,

and address signals will all have roughly the same pad and flight delays to travel to the

memory, the rising edge of the clock at the memory will be centered with the command and

address signals, allowing reliable capture. To ensure proper memory read write sequences

the DDR memory controller contains a delay compensation circuit that, in conjunction with

I/O cell circuitry, can be used to meet the memory target timing requirements. The delay

compensation circuit offers the following features:

Programmable read clock delay specified as a percentage of a clock cycle:

The Read transfer path, should also take into account the memory flight paths. There is a

certain time lag from when the clock is sent from the memory controller to when the data

and DQS signals are received at the memory controller from the memory. Since the DQS

from the memory will be sent coincident with the data, and the data must be captured

reliably, the DQS signal is delayed through the register field dll_dqs_delay_X so that it is

centered in the data valid window (nominally approximately 1/4 cycle).

Programmable write clock and write DQS delays specified as percentages of a

clock cycle:

The Write transfer path is controlled from the dqs_out_shift and wr_dqs_shift register

parameters which set the delay for the DQS signal for dll_wr_dqs_slice and for the clk_wr

signal, respectively. These parameters should be programmed such that clk_dqs_out is in

phase with clk and that clk_wr is 1/4 cycle ahead of clk_dqs_out.

Delay compensation circuit re-sync circuitry activated during refresh cycles to

compensate for temperature and voltage drift:

Chip Select

Row

Bank

Column

Data Path

29 28

28 27

16 15

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