AD6676EBZ datasheet(45/90 Pages) AD

45 / 90 page

Data Sheet

AD6676

Rev. A | Page 45 of 90

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

10.0

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

11.0

TIME (µs)

AD6676

ENTERS STANDBY

WITHIN 100ns

Figure 115. Fast Power-Down Response When the AD6676 Is Placed in

Standby

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

TIME (µs)

1% SETTLING TIME = 2.5µs

Figure 116. Settling Time for STDBY_FAST with the STBY_VSS2GEN Enabled

for Fastest Recovery, Approximately 2.5 µs to 1 %

1.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

TIME (µs)

1% SETTLING TIME = 11.5µs

Figure 117. Settling Time for STDBY_SLOW with STBY_VSS2GEN in Standby

for Additional Power Savings, Approximately 11.5 µs to 1 %

INTRODUCTION TO THE JESD204B INTERFACE

The JESD204B interface reduces the PCB area for data interface

routing yet enabling the use of smaller packages for converter

and logic devices. The AD6676 digital output complies with the

JEDEC Standard No. JESD204B, Serial Interface for Data

Converters. JESD204B is a protocol to link the AD6676 to a

digital processing device over a serial interface. The AD6676

supports link rates of up 5.333 Gbps while operating with two

output lanes in support of a maximum I/Q data rate (fDATA_IQ)

of 266.67 MSPS. Note that a two output lane configuration is

always required for decimation factors of 12 and 16.

JESD204B Overview

JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special

characters during the initial establishment of the link and

additional synchronization is embedded in the data stream

thereafter. A JESD204B receiver is required to complete the

serial link. For additional details on the JESD204B interface,

refer to the JESD204B standard.

Because the AD6676 provides 16-bit complex IQ data, its

JESD204B transmit block effectively maps the output of two

virtual ADCs (M = 2) over a link. The link is configurable for

either single or dual lanes with each lane providing a serial data

stream via a differential output. The JESD204B specification

refers to a number of parameters to define the link and these

parameters must match between the AD6676 JESD204B

transmitter and receiver.

The following parameters describe a JESD204B link:

•

S = samples transmitted per single converter per frame

cycle (AD6676 value = 1)

•

M = number of converters per converter device (AD6676

value = 2)

•

L = number of lanes per converter device (AD6676 value

can be 1 or 2)

•

N = converter resolution (AD6676 value = 16)

•

N’ = total number of bits per sample (AD6676 value = 16)

•

CF = number of control words per frame clock cycle per

converter device (AD6676 value = 0)

•

CS = number of control bits per conversion sample

(AD6676 value = 0)

•

K = number of frames per multiframe (configurable on the

AD6676 up to 32)

•

HD = high density mode (AD6676 value = 0)

•

F = octets per frame (AD6676 value = 2 or 4, dependent on

L = 2 or 1)

•

T = tail bit (AD6676 value = 0)

•

SCR = scrambler enable or disable (configurable on the

AD6676)

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