AD6676EBZ datasheet(28/90 Pages) AD

28 / 90 page

AD6676

Data Sheet

Rev. A | Page 28 of 90

1.0

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

SAMPLES

ZOOM-IN OF LARGE SCALE

SETTLING RESPONSE FOR 1% SETTLING

LARGE SCALE SETTLING

NO OVERLOAD/

RECOVERY

OVERLOAD/

RECOVERY

6 SAMPLES

@ 266.7MSPS

Figure 78. Comparison of Normalized IQ Magnitude Response for Decimate

by 24 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and

Above Peak Power Level, Resulting in ADC Overload

1.1

1.2

1.0

0.98

0.99

1.00

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

SAMPLES

ZOOM-IN OF LARGE SCALE

SETTLING RESPONSE FOR 1% SETTLING

LARGE SCALE SETTLING

NO OVERLOAD/

RECOVERY

OVERLOAD/

RECOVERY

5 SAMPLES

@ 100MSPS

Figure 79. Comparison of Normalized IQ Magnitude Response for Decimate

by 32 Case When a Pulsed CW Waveform (10 ns Width) Is Just Below and

Above Peak Power Level, Resulting in ADC Overload

Σ-Δ ADC CONFIGURATION CONSIDERATIONS

Maximum Input Power (PIN_0dBFS and IDAC1FS)

The AD6676 maximum full-scale input power (PIN_0dBFS) for

a sinusoidal input signal is dependent on the IDAC1 peak full-

scale output current (IDAC1FS) and the RIN of the attenuator

(that is, 60 Ω) as shown in the equation below.

PIN_0dBFS = 10 × log10(1/2 × RIN × IDAC1FS2)

(2)

The derivation of this equation becomes apparent when

considering the AD6676 input stage consisting of RESON1,

IDAC1, and RIN, as shown in Figure 68. RIN is the input resistance

of the attenuator. The cascode transistor associated with IDAC1

and RIN establishes a low impedance node serving as a current

mode summing junction whereby the input signal (equal to

VIN±/RIN) is compared to the feedback signal from IDAC1.

Note that the feedback loop of the Σ-Δ modulator attempts to

generate an equal but opposite feedback current to cancel the

signal current appearing at this summing junction. Ultimately,

the maximum feedback signal current that can be generated by

IDAC1 is limited by its full-scale setting, IDAC1FS, thus setting

the 0 dBFS level on which feedback can no longer cancel any

further increase in input signal level (or power). For example,

the AD6676 nominal setting for IDAC1FS at 4 mA equates to a

PIN_0dBFS of −3 dBm, resulting in a differential voltage swing

of ±240 mV peak.

Equation 2 assumes that the attenuator setting is 0 dB. Any

setting beyond 0 dB increases the effective PIN_0dBFS measured at

the input of the attenuator by an amount equal to the attenuator

setting.

In practice, the actual measured PIN_0dBFS may vary a few tenths

of a decibel for different application parameter settings due to some

amount of pass band tilt. For this reason, PIN_0dBFS is defined at

the IF center.

LEXT Selection

The range of permissible values for LEXT depends on the following

application parameters: FIF, FADC, and IDAC1FS. Figure 80 shows

the upper and lower settings (LMAX and LMIN) when IDAC1FS is

set to its default settings of 4 mA. Note that the LMAX limit is set

by the largest voltage swing across the LC tank and the LMIN

limit is set by the maximum tuning capacitance available from

an internal capacitor array.

200

100

200

300

400

500

150

250

350

450

FIF (MHz)

ABSOLUTE MAXIMUM

MAXIMUM FOR FADC = 3.2GHz

MAXIMUM FOR FADC = 2.6GHz

MAXIMUM FOR FADC = 2.0GHz

MINIMUM

Figure 80. Maximum External Inductor Value as a Function of IF Frequency

and Clock Rate for IDAC1FS = 4 mA

Note the following points when selecting LEXT:

•

Larger values of LEXT result in larger voltage swings across

the LC tank. Selecting a value that is approximately 55% to

80% of the LMAX value can be considered with a lower value,

typically resulting in improved IMD performance due to

reduced voltage swing across the inductor. Conversely, a

higher value may lead to a slight improvement in noise

performance (mostly near the IF center), but at the expense

of IMD performance.

•

Inductor accuracy of 10% is sufficient because it falls well

within the calibration range of the AD6676 during its

initialization phase on power-up.

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