AD6676EBZ datasheet(23/90 Pages) AD

23 / 90 page

Data Sheet

AD6676

Rev. A | Page 23 of 90

THEORY OF OPERATION

OVERVIEW

The AD6676 is a highly integrated and flexible IF subsystem

capable of digitizing IF signals. The ability to tune the IF

frequency and bandwidth allows the Σ-Δ ADC to be optimized

for different applications while trading off bandwidth for dynamic

range. To facilitate its evaluation and design in, a software tool

that is part of the AD6676EBZ development platform must be

used to configure and evaluate the device. This tool saves the

SPI initialization and configuration sequence to a file for later

use. A screenshot of the GUI front panel (see Figure 66) shows the

different user specified application parameters that configure

the AD6676. The following discussion provides more insight

into the device operation and how these application parameters

affect performance.

Figure 66. Screenshot of AD6676 GUI Software Tool that Facilitates Device

Configuration and Evaluation

A functional block diagram of the AD6676 is shown Figure 67.

The focal point of the AD6676 is its continuous time, band-pass

Σ-Δ ADC that operates with a clock rate between 2.0 GHz and

3.2 GHz. An on-chip controller configures the Σ-Δ ADC based

on the user specified application parameters. The Σ-Δ ADC

provides exceptional dynamic range and pass band flatness

within the desired IF span while limiting out-of-band peaking

to less than 0.5 dB. An on-chip clock synthesizer supplies a

2.94 GHz to 3.2 GHz Σ-Δ ADC clock. Alternatively, an external

clock can be supplied for lower clock rates or improved phase

noise performance.

On-chip digital signal processing blocks include a quadrature

digital downconverter (QDDC) followed by selectable decimation

filters supporting decimation factors of 12, 16, 24, or 32. The

QDDC performs a complex shift of the desired IF pass band

such that it is centered about dc, that is, zero IF. Cascaded

decimation filters remove the inherent out-of-band noise of the

ADC along with any other out-of-band signal content such that

the 16-bit complex IQ data is reduced to a more manageable data

rate for transfer to the host via a single or dual lane JESD204B

interface supporting up to 5.333 Gbps lane rates.

The AD6676 also includes features for AGC support and/or level-

planning optimization. AGC support includes the ability to

monitor peak power at the Σ-Δ ADC output or rms power after

the first internal decimation stage. The host can initiate fast AGC

action by configuring various flags whose status are made available

on the AGC4 to AGC1 pins. Flags can be set with programmable

thresholds indicating whether the signal level is above or below

a defined level. A 27 dB attenuator with a step size of 1 dB is

available for IF AGC control or level planning optimization during

initial system calibration. Alternatively, the nominal 0 dBFS

full-scale input power level (PIN_0dBFS) of −2 dBm can be

reduced by up to 12 dB thus further reducing the RF/IF gain

requirements. The SPI programs numerous parameters of the

AD6676, allowing the device to be optimized for a variety of

applications.

L–

L+

RESETB

VDDIO

AGC4, AGC3

AGC2, AGC1

VDD2NV

VSSA

VDD2

VDDD VSSD

SPI

CSB

SCLK

SDIO

SDO

SERDOUT0+

SERDOUT0–

SERDOUT1+

SERDOUT1–

VDDHSI

SYNCINB±

SYSREF±

AGC

SUPPORT

CLOCK

GENERATION

–2.0V

REG

M = 12,

16, 24,

QDDC +

NCO

BAND-PASS

Σ-Δ ADC

VIN–

VIN+

27dB ATTENUATOR

(1dB STEPS)

CLOCK

SYNTHESIZER

JESD204B

SUBCLASS 1

CONTROL

CLK+ CLK–

VDDC

VDDQ

AD6676

VDDL VDD1

VSS2OUT

VSS2IN

Figure 67. Functional Block Diagram

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