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AD6676EBZ 数据表(PDF) 89 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 89 Page - Analog Devices |
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89 / 90 page  Data Sheet AD6676 Rev. A | Page 89 of 90 JESDSYN Status Register Address: 0x2DC, Reset: 0x80, Name: JESDSYN_STATUS Table 130. Bit Descriptions for JESDSYN_STATUS Bits Bit Name Description Reset Access [7:4] RESERVED 0x8 R 3 PLL_LCK JESD204 PLL Synthesizer Lock Bit (1 = lock). 0x0 R 2 RESERVED 0x0 R 1 VCO CAL BUSY VCO Calibration Busy (0 = done). 0x0 R 0 CP CAL DONE Charge Pump Calibration Done (1 = done). 0x0 R Shuffler Control Register Address: 0x340, Reset: 0x03, Name: SHUFFLE_CTRL Table 131. Bit Descriptions for SHUFFLE_CTRL Bits Bit Name Description Reset Access [7:2] RESERVED 0x00 RW 1 RESERVED 1 RW 0 EN_ADAPTIVE_SHUFFLE Enable Adaptive Flash Shuffling. 1 RW Shuffler Threshold 1 and 2 Register Address: 0x342, Reset: 0xF5, Name: SHUFFLE_THREG_0 Table 132. Bit Descriptions for SHUFFLE_THREG_0 Bits Bit Name Description Reset Access [7:4] SHUFFLE_TH2 Threshold value for shuffling every two cycles. Shuffle-every-2 is triggered when the ADC data is greater than or equal to this threshold. 0xF R [3:0] SHUFFLE_TH1 Threshold value for shuffling every one cycle. Shuffle-every-1 is triggered when the ADC data is greater than or equal to this threshold 0x5 R Shuffler Threshold 3 and 4 Register Address: 0x343, Reset: 0xFF, Name: SHUFFLE_THREG_1 Table 133. Bit Descriptions for SHUFFLE_THREG_1 Bits Bit Name Description Reset Access [7:4] SHUFFLE_TH4 Threshold value for shuffling every four cycles. Shuffle-every-4 is triggered when the ADC data is greater than or equal to this threshold. 0xF R [3:0] SHUFFLE_TH3 Threshold value for shuffling every three cycles. Shuffle-every-3 is triggered when the ADC data is greater than or equal to this threshold 0xF R |
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