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AD6676EBZ 数据表(PDF) 82 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 82 Page - Analog Devices |
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82 / 90 page  AD6676 Data Sheet Rev. A | Page 82 of 90 JESD204 FCHK0 Register Address: 0x1D8, Reset: 0x44, Name: FCHK0 Table 102. Bit Descriptions for FCHK0 Bits Bit Name Description Reset Access [7:0] FCHK0 Checksum for Lane 0. 0x44 RW JESD204 FCHK1 Register Address: 0x1D9, Reset: 0x45, Name: FCHK1 Table 103. Bit Descriptions for FCHK1 Bits Bit Name Description Reset Access [7:0] FCHK1 Checksum for Lane 1. 0x45 RW Enable Lane FIFO Register Address: 0x1E0, Reset: 0x00, Name: EN_LFIFO Table 104. Bit Descriptions for EN_LFIFO Bits Bit Name Description Reset Access [7:1] RESERVED 0x00 RW 0 EN_LFIFO Lane FIFO Enable. Once the entire configuration of the framer has been completed, and the link is powered up, set this bit to start the lane FIFOs that manage the hand-off of data from the framer to the transmitter PHY. 0x0 RW Swap Register Address: 0x1E1, Reset: 0x00, Name: SWAP Table 105. Bit Descriptions for SWAP Bits Bit Name Settings Description Reset Access [7:6] RESERVED 0x0 RW [5:4] SWAP_CONV Bit [4] swaps the source of Framer Converter 0 (default is I channel). 0x0 RW Bit [5] swaps the source of Framer Converter 1 (default is Q channel). 00 Framer Input 1 = Q channel; Framer Input 0 = I channel 01 Framer Input 1 = Q channel; Framer Input 0 = Q channel 10 Framer Input 1 = I channel; Framer Input 0 = I channel 11 Framer Input 1 = I channel; Framer Input 0 = Q channel [3:2] RESERVED 0x0 RW [1:0] SWAP_LANE Bit [0] swaps the source of physical output lane 0. 0x0 RW Bit [1] swaps the source of physical output lane 1. 00 Output Lane 1 = Famer lane 1; Output Lane 0 = Framer Lane 0 01 Output Lane 1 = Framer lane 1; Output Lane 0 = Framer Lane 1 10 Output Lane 1 = Framer lane 0; Output Lane 0 = Framer Lane 0 11 Output Lane 1 = Framer lane 0; Output Lane 0 = Framer Lane 1 |
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