AD6676EBZ datasheet(59/90 Pages) AD

59 / 90 page

Data Sheet

AD6676

Rev. A | Page 59 of 90

POWERING THE AD6676

The AD6676 requires the following analog and digital power

supplies with no restrictions on the power supply sequencing order:

•

An analog 2.5 V and 1.1 V supply

•

A digital 1.1 V and digital input/output supply of 1.8 V to 2.5 V

The current consumption from the different analog and digital

supply domains does not vary much over the specified 2.0 GHz

to 3.2 GHz ADC clock rate range nor the digital decimation factor

and number of JESD204B lanes used. Table 24 shows the

dependency of a typical device as these settings are modified with

the IF and BW remaining fixed at 250 MHz and 75 MHz,

respectively.

Figure 142 shows the recommended method used on the

AD6676EBZ where a universal 3.3 V supply is available. Note

that various analog and digital supply domains within the

AD6676 are grouped together to reduce the external LDO

requirements. A high efficiency step-down regulator, such as

the ADP2164, is used to generate a 1.6 V output that drives

separate low drop-out LDOs for the analog VDD1 and digital

VDDD supplies.

ADP2164

ADP1752-2.5

ADP1752-1.8

ADP1752-1.1

VDDD, VDDHSI

VDD2, VDD2NV

VDDIO

ADP1752-1.1

VDD1, VDDL, VDDC, VDDQ

1.6V

3.3V

Figure 142. Low Noise Power Solution for the AD6676

Separate LDOs for the 1.1 V analog and digital supplies provide

greater isolation between these critical supply domains as well

as reduce the IR drops across ferrite beads that provide further

isolation. High quality LDOs that exhibit better PSSR characteristics

at the switching regulators operating frequency are preferable.

Note that the digital VDDIO supply of the AD6676 is only used

for the CMOS SPI and AGCx input/output pins thus it can be

tied to the same supply domain used by the host that is connected

to these pins. Alternatively, the ADP223 dual output LDO can

be used instead of the ADP1752-2.5 and ADP1752-1.8.

On the analog 1.1 V supply, amplitude modulation can result in

phase modulation via the clock supplies of the AD6676 (VDDC,

VDDQ).

Table 24. Current Consumption Variation as FADC Is Varied from 3.2 GHz to 2.0 GHz

Supply Current

Conditions

CLK

Unit

3.2 GHz

2.8 GHz

2.4 GHz

2.0 GHz

VDD1+ IVDDL

Not applicable

371

364

357

351

VDDC + IVDDQ

Not applicable

VDD2 + IVDD2NV

Not applicable

143

140

139

VDDD

Decimate by 16

152

144

131

100

Decimate by 32

155

150

135

106

VDDHSI

Two lane

168

158

One lane

166

167

161

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