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AD6676EBZ 数据表(PDF) 69 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 69 Page - Analog Devices |
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69 / 90 page  Data Sheet AD6676 Rev. A | Page 69 of 90 Chip Grade/Revision Register Address: 0x006, Reset: 0x00, Name: GRADE_REVISION Table 37. Bit Descriptions for GRADE_REVISION Bits Bit Name Description Reset Access [7:4] REVISION 0x0 R [3:0] GRADE 0x0 R Vendor ID 0 Register Address: 0x00C, Reset: 0x56, Name: VENDOR_ID0 Table 38. Bit Descriptions for VENDOR_ID0 Bits Bit Name Description Reset Access [7:0] VENDOR_ID0 0x56 R Vendor ID 1 Register Address: 0x00D, Reset: 0x04, Name: VENDOR_ID1 Table 39. Bit Descriptions for VENDOR_ID1 Bits Bit Name Description Reset Access [7:0] VENDOR_ID1 0x04 R ADC CLK Frequency LSB Register Address: 0x100, Reset: 0x10, Name: FADC_0 Table 40. Bit Descriptions for FADC_0 Bits Bit Name Description Reset Access [7:0] FADC_0 Lower 8-bits of 16-bit value that defines the ADC CLK frequency to 1 MHz resolution. For example, the FADC_1 and FADC_0 settings for a 3200 MHz CLK frequency are 0x0C and 0x80, respectively. 0x10 RW ADC CLK Frequency MSB Register 1 Address: 0x101, Reset: 0x0E, Name: FADC_1 Table 41. Bit Descriptions for FADC_1 Bits Bit Name Description Reset Access [7:0] FADC_1 Upper 8-bits of 16-bit value that defines the ADC CLK frequency to 1 MHz. For example, the FADC_1 and FADC_0 settings for a 3200 MHz CLK frequency are 0x0C and 0x80, respectively. 0x0E RW IF Frequency LSB Register 0 Address: 0x102, Reset: 0x2C, Name: FIF_0 Table 42. Bit Descriptions for FIF_0 Bits Bit Name Description Reset Access [7:0] FIF_0 Lower 8-bits of 16-bit value that defines the target IF frequency to 1 MHz resolution. For example, the FIF_1 and FIF_0 settings for a 300 MHz IF frequency are 0x01 and 0x2C, respectively. 0x2C RW |
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