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AD6676EBZ 数据表(PDF) 86 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 86 Page - Analog Devices |
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86 / 90 page  AD6676 Data Sheet Rev. A | Page 86 of 90 PHY Control 3 Register Address: 0x1EF, Reset: 0x00, Name: PRE-EMPHASIS Table 117. Bit Descriptions for PRE-EMPHASIS Bits Bit Name Description Reset Access 7 SER_EMP_PS1 Toggle Polarity of Lane 1 Emphasis. 0x0 RW [6:4] SER_EMP_IDAC1 Lane 1 IDAC Setting. 0x0 RW 00: 0 mV emphasis differential p-p. 01: 160 mV emphasis differential p-p. 10: 80 mV emphasis differential p-p. 11: 40 mV emphasis differential p-p. 3 SER_EMP_PS0 Toggle polarity of Lane 0 emphasis. 0x0 RW [2:0] SER_EMP_IDAC0 Lane 0 IDAC Setting. 0x0 RW 00: 0 mV emphasis differential p-p. 01: 160 mV emphasis differential p-p. 10: 80 mV emphasis differential p-p. 11: 40 mV emphasis differential p-p. ADC Standby 0 Register Address: 0x250, Reset: 0xFF, Name: STBY_DAC Table 118. Bit Descriptions for STBY_DAC Bits Bit Name Description Reset Access [7:0] STBY_DAC Setting register to 0x95 results in faster standby ADC recovery time. 0xFF RW CLKSYN Enable Register Address: 0x2A0, Reset: 0x00, Name: CLKSYN_ENABLE Table 119. Bit Descriptions for CLKSYN_ENALBE Bits Bit Name Description Reset Access 7 EN_EXTCK EXTCK Enable. 0x0 RW 6 EN_ADC_CK ADC CK Enable. 0x0 RW 5 EN_SYNTH Synthesizer Enable. 0x0 RW 4 EN_VCO_PTAT VCO PTAT Enable. 0x0 RW 3 EN_VCO_ALC VCO ALC Enable. 0x0 RW 2 EN_VCO VCO Enable. 0x0 RW 1 EN_OVERIDE_CAL Override Calibration Enable. 0x0 RW 0 EN_OVERIDE Override Enable. 0x0 RW CLKSYN Integer N LSB Register Address: 0x2A1, Reset: 0x80, Name: CLKSYN_INT_N_LSB Table 120. Bit Descriptions for CLKSYN_INT_N_LSB Bits Bit Name Description Reset Access [7:0] INT_N_LSB Lower LSBs of 11-bit Integer-N Value. 0x80 RW |
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