AD6676EBZ datasheet(65/90 Pages) AD

65 / 90 page

Data Sheet

AD6676

Rev. A | Page 65 of 90

The AD6676 serial port can support both most significant bit

(MSB) first and least significant bit (LSB) first data formats.

Figure 147 illustrates how the serial port words are formed for

the MSB first and LSB first modes. The bit order is controlled

by the LSB_FIRST bit (Register 0x000, Bit 6). The default value

is 0, MSB first. When the LSB_FIRST bit is set high, the serial

port interprets both instruction and data byte LSBs first.

SCLK

SDATA

R/W

A0 D71 D61

D1N D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

CSB

A14 A13

SCLK

SDATA

R/W

D71

D61

D1N

D0N

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

CSB

A14

Figure 147. SPI Timing, MSB First (Upper) and LSB First (Lower)

Figure 148 illustrates the timing requirements for a write

operation to the SPI port. After the serial port enable (CSB)

signal goes low, data (SDIO) pertaining to the instruction

header is read on the rising edges of the clock (SCLK). To

initiate a write operation, the read/not write bit is set low. After

the instruction header is read, the eight data bits pertaining to

the specified register are shifted into the SDIO pin on the rising

edge of the next eight clock cycles.

Figure 149 illustrates the timing for a 3-wire read operation to

the SPI port. After CSB goes low, data (SDIO) pertaining to the

instruction header is read on the rising edges of SCLK. A read

operation occurs if the read/not write indicator is set high. After

the address bits of the instruction header are read, the eight data

bits pertaining to the specified register are shifted out of the

SDIO pin on the falling edges of the next eight clock cycles.

Figure 150 illustrates the timing for a 4-wire read operation to

the SPI port. The timing is similar to the 3-wire read operation

with the exception that data appears at the SDO pin only,

whereas the SDIO pin remains at high impedance throughout

the operation. The SDO pin is an active output only during the

data transfer phase and remains three-stated at all other times.

Lastly, the SPI port must not be active during periods when the

full dynamic performance of the converter is required. Because

the SCLK, CSB, and SDIO signals are typically asynchronous to

the ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD6676 to keep these signals from transitioning at the converter

input pins and causing unwanted spurious signals.

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

CSB

A13

Figure 148. SPI Write Operation Timing

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

tACCESS

CSB

Figure 149. SPI 3-Wire Read Operation Timing

CSB

A14

SCLK

SDIO

tSCLK

tLOW

tHIGH

tDS

tDH

R/W

tACCESS

SDO

Figure 150. SPI 4-Wire Read Operation Timing

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