AD6676EBZ datasheet(63/90 Pages) AD

63 / 90 page

Data Sheet

AD6676

Rev. A | Page 63 of 90

Table 27. SPI CLK SYN Initialization Example, fCLK = 2.94912 GHz, fREF = 122.88 MHz (Suitable for Decimation by 24)

Step

Address (Hex)1

Write Value1

Comments

0x2A1

0x60

Set the integer-N value.

0x2A2

0x00

Set the integer-N value.

0x2A5

0x08

Reset VCO calibration.

0x2AC

0x18

Set the charge pump current (see Table 12).

0x2B7

0xF0

Configure VCO.

0x2BB

0x7D

Set the reference divider to DIV = 2, such that f

PFD = 61.44 MHz (see Table 11).

0x2A0

0x7D

Enable CLKSYN and the ADC clock.

0x2AB

0xC5

Start VCO calibration.

Wait at least 400 ns because f

PFD = 50 MHz.

0x2AD

0x80

Start charge pump calibration.

Wait at least 800 ns because f

PFD = 50 MHz.

1 Cells in the Address (Hex) column and Write Value column were left intentionally blank.

Table 28. SPI fCLK Initialization

Step

Address

Write Value

Comments

0x2A5

0x05

Select RF clock path

0x2A0

0xC0

Enable RF clock receiver and ADC clock

Table 29. SPI AGC Initialization Example

Step

Address

Write Value

Comments

0x181

0x00

Set ATTEN_VALUE_PIN0 to 0 dB.

0x182

0x06

Set ATTEN_VALUE_PIN1 to 6 dB.

0x19E

0x13

Enable FLAG1 and 0 on AGC4 and AGC3 pins, respectively. Also, logical OR of ADC reset with a

peak detect threshold flag.

0x19B

0x04

Select AGC Flag 0 above Peak Threshold 0.

0x19C

0x06

Select AGC Flag 1 below low threshold.

0x193

0x00

Peak Threshold 0 set to −3 dBFS.

0x194

0x0d

Peak Threshold 0 set to −3 dBFS.

0x197

0x00

Low Threshold set to −15 dBFS.

0x198

0x09

Low Threshold set to −15 dBFS.

0x199

0x01

Low threshold dwell time mantissa.

0x19A

0x02

Low threshold dwell time exponent.

Table 30. SPI Shuffler Initialization Example

Step

Address

Write Value

Comments

0x342

0x3F

Shuffle every two clock cycles with a threshold of 3.

0x343

0xFF

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