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AD6676EBZ 数据表(PDF) 5 Page - Analog Devices |
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AD6676EBZ 数据表(HTML) 5 Page - Analog Devices |
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5 / 90 page  Data Sheet AD6676 Rev. A | Page 5 of 90 SPECIFICATIONS VDD1 = VDDL = VDDC = VDDQ = 1.1 V, VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, FIF = 250 MHz, BW = 75 MHz, FADC = 3.2 GHz, attenuator = 0 dB, L± (inductor values) = 19 nH, maximum PIN_0dBFS setting with IDAC1FS = 4 mA, fDATA_IQ = 200 MSPS, shuffler enabled (every clock cycle) with default threshold of 5, unless otherwise noted. Table 1. Parameter Temperature Test Conditions/Comments Min Typ Max Unit SYSTEM DYNAMIC PERFORMANCE Full-Scale Input Power Level (PIN_0dBFS)1 −2 dBm Maximum Continuous Wave (CW) Input Power2 −2 −1 dBFS Noise Figure (NF) No signal and measured 17 dB Worst In-Band Noise Spectral Density Full Over a 5 MHz bandwidth −155 −152.5 dBFS/Hz Noise Figure at IF Center (NF) No signal and measured 13 dB In-Band Noise Spectral Density (NSD) Over a 5 MHz bandwidth −159 dBFS/Hz Input Second-Order Intercept (IIP2) −6 dBFS tones 60 dBm Second-Order Intermodulation Distortion (IMD) (IMD2) See Table 20 −68.3 dBc Input Third-Order Intercept (IIP3) Full −8 dBFS tones 36.9 dBm Third-Order IMD (IMD3) Full −8 dBFS tones −95 −84.2 dBc Worst In-Band Spur for Swept CW Tone Full −2 dBFS tone −99 −93.5 dBFS −10 dBFS tone −109.6 dBFS In-Band Noise Full −2 dBFS tone −75.5 −73.7 dBFS Full No CW tone −78.5 −76.5 dBFS Gain Variation Full 0.5 dB IF INPUT (VIN±) Input Span 0 dBFS 0 dB Attenuator Setting 0.48 V p-p 12 dB Attenuator Setting 1.92 V p-p Common-Mode Input Voltage Self biased 1.0 V Differential Input Impedance 25°C 60||2 Ω||pF Common-Mode Input Impedance 25°C 3.5 kΩ Full-Scale Input Power Adjustment (PIN_0dBFS) IDAC1 FS span of 1 mA to 4 mA 12 dB DIGITAL STEP ATTENUATOR (VIN±) Attenuation Range Full 27 dB Step Size Full 1 dB Input Return Loss Full 20 dB Input Return Loss Variation vs. Attenuator Setting Full 2 dB CLOCK INPUT (CLK±) Clock Synthesizer Disabled Frequency Range Full 2.0 3.2 GHz Amplitude Range Full 0.4 0.8 2.0 V p-p Differential Input Impedance 25°C At 3 GHz 86||0.3 Ω||pF Common Mode Impedance 25°C At 3 GHz 700||0.8 Ω||pF Input Return Loss 25°C With 1:2 balun 15 dB Common-Mode Voltage 25°C Self biased 0.70 V Clock Synthesizer Enabled Frequency Range3 Full 10 320 MHz Amplitude Range Full Single-ended into CLK+ 0.4 0.8 1.1 V p-p CLK+ Input Impedance 25°C 1.4||1.0 kΩ||pF Minimum Slew Rate 12 V/µs Common-Mode Voltage 25°C Self biased 0.55 V |
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