AD6676EBZ datasheet(64/90 Pages) AD

64 / 90 page

AD6676

Data Sheet

Rev. A | Page 64 of 90

SERIAL PORT INTERFACE (SPI)

SPI REGISTER MAP DESCRIPTION

The AD6676 contains a set of programmable registers (described in

the Register Memory Map section) that initialize and configure the

device for its intended application. Note the following points

when programming the AD6676 SPI registers:

•

Registers pertaining to similar functions are typically

grouped together and assigned adjacent addresses.

•

Bits that are undefined within a register must be assigned a

0 when writing to that register.

•

Do not write to registers that are undefined.

•

A hardware or software reset is recommended on power-

up to place SPI registers in a known state.

A SPI initialization routine is required as part of the boot

process. See Table 26 for an example procedure.

Reset

Issuing a hardware or software reset places the AD6676 SPI

registers in a known state. Both types of resets are similar in

that they place SPI registers to their default states as described

in Table 32, with the notable exception that a software reset

does not affect Register 0x000. A hardware reset can be issued

from a host or external supervisory IC by applying a low pulse

with a minimum width of 40 ns to the RESETB pin (Pin G6).

RESETB can also kept be left open if unused because it has an

internal pull-up resistor. After issuing a reset, the SPI initialization

process need only write to registers that are required for the

boot process as well as any other register settings that must be

modified, depending on the target application.

Although the AD6676 does feature an internal power on reset

(POR), it is still recommended that a software or hardware reset

be implemented shortly after power-up. The internal reset

signal is derived from a logical OR operation from the internal

POR signal, the RESETB pin, and the software reset state. A self

clearing software reset can be issued via the reset bit (Register 0x00,

Bit 7). It is also recommended that the bit settings for Bits[7:4]

be mirrored onto Bits[3:0] for the instruction cycle that issues a

software reset.

Table 31. SPI Registers Pertaining to SPI Options

Address (Hex)

Bit

Description

0x000

Software reset SPI

Enable SPI LSB first

Enable 4-wire

SPI OPERATION

The serial port of the AD6676 shown in Figure 146 has a 3- or

4-wire SPI capability, allowing read/write access to all registers

that configure the internal parameters of the device. It provides

a flexible, synchronous serial communications port, allowing easy

interface to most industry-standard FPGAs and microcontrollers.

The 1.8 V to 2.5 V serial input/output is compatible with most

synchronous transfer formats.

AD6676

SPI PORT

SDO (PIN H6)

SDIO (PIN K8)

SCLK (PIN K7)

CSB (PIN J6)

Figure 146. AD6676 SPI Port

The default 4-wire SPI interface consists of a clock (SCLK),

serial port enable (CSB), serial data input (SDIO), and serial

data output (SDO). The inputs to SCLK, CSB, and SDIO contain

a Schmitt trigger centered about VDDIO/2. The maximum

frequency for SCLK is 40 MHz. The SDO pin is active only

during the transmission of data and remains three-stated at any

other time.

A 3-wire SPI interface can be enabled by clearing the SDIO_DIR

bit (Register 0x000, Bit 4). This causes the SDIO pin to become

bidirectional such that output data only appears on the SDIO

pin during a read operation. The SDO pin remains three-stated

in a 3-wire SPI interface.

Instruction Header Information

MSB

LSB

I_15

I_14

I_13

I_12

…

I_01

I_00

R/W

A14

A13

A12

…

A 16-bit instruction header must accompany each read and write

operation. The MSB is a R/W indicator bit with logic high

indicating a read operation. The remaining 15 bits specify the

address bits to be accessed during the data transfer portion. The

eight data bits immediately follow the instruction header for

both read and write operations. For write operations, registers

change immediately on writing to the last bit of each transfer byte.

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