AD6676EBZ datasheet(24/90 Pages) AD

24 / 90 page

AD6676

Data Sheet

Rev. A | Page 24 of 90

RIN

VIN

CARRAY

LEXT

RESON1

RESON2

RESON3

IDAC1FS

ADJUST

G31

G43

G54

G65

–G34

–G56

G53

17-LEVEL

FLASH

ADC

OPTIONAL

SHUFFLER

ENCODER

DOUT

Figure 68. Simplified Single-Ended Representation of the Band-Pass Σ-Δ ADC Modulator

BAND-PASS Σ-Δ ADC ARCHITECTURE

Figure 68 shows a simplified single-ended representation of the

AD6676 band-pass Σ-Δ ADC. It is a sixth-order modulator

consisting of three cascaded second-order continuous-time

resonators with feedback DACs and an oversampling quantizer.

The first resonator (RESON1) is based on a LC tank with its

resonant frequency tuned via CARRAY to the IF center while the

second and third resonators (RESON2 and RESON3) are active

RC-based with their resonant frequencies tuned to frequencies

offset symmetrically about the IF. These resonant frequencies

correspond to the zero locations of the Σ-Δ ADC quantization

noise and are set according to the user defined IF frequency

and bandwidth.

A 17-level flash ADC oversamples the analog output of RESON3

with the digital output of the flash ADC feeding back to each of

the resonators via current mode DACs (IDACx). Note that because

the ADC thermometer code output can range from −8 to +8, it is

represented by five bits that are passed to the AD6676 digital path.

The IDAC1 full-scale current setting (IDAC1FS) sets the maximum

full-scale input power level (PIN_0DBFS). The full-scale settings of

the other IDACs set the pole location of the modulator to achieve a

flat pass band response. Lastly, a programmable shuffler follows

the flash ADC to improve the linearity performance of the

AD6676 under large signal conditions.

The tunable nature of the Σ-Δ ADC is a result of the full-scale

current of the feedback DACs, as well as the conductances (G)

and capacitances (C) associated with each resonator. The value

of these programmable components are calculated from the

user specified application parameters listed in Table 7. The

impact of each of these parameters on the performance of the

AD6676 is described in subsequent sections.

Table 7. List of User Specified Application Parameters That

Determine the Σ-Δ ADC Internal Settings

Application

Parameter

Description

SPI Register(s)

IF center frequency in MHz

0x102, 0x103

IF pass band bandwidth in MHz

0x104, 0x105

ADC

Σ-Δ ADC clock rate in MHz

0x100, 0x101

EXT

External inductor value in nH

0x106

MRGN

Margin offset to set resonator

frequency in MHz

0x107 to 0x109

IDAC1

Full-scale current of IDAC1 that

sets PIN_0dBFS level

0x10A

The on-chip controller is used only during device initialization

and performs the following tasks:

•

Power-up negative regulator (used by IDACs)

•

Calibrate RESON1 and 17-level flash ADC

•

Tune Σ-Δ ADC based on user input parameters

•

Set up PLL used by JESD204B PHY

After device initialization, the on-chip controller is disabled; it

is not used during normal device operation.

Signal and Noise Transfer Functions

The frequency domain response of a Σ-Δ ADC is defined by its

signal and noise transfer functions (STF and NTF). Figure 69

shows a simplified feedback model of a Σ-Δ modulator with the

ADC quantization error modeled as an additive noise source

(E) after the loop filter (H). The STF is the frequency response

of the output signal (V) relative to a swept single tone at its input

(U) while the NTF is the frequency response of the ADC

quantization noise (that is, V/E) that undergoes noise shaping

due to of the loop filter of the ADC. Note that the ADC and

DACs within the feedback loop operate at a much higher clock

rate than a traditional open-loop ADC in which only the

Nyquist criterion must be satisfied (FADC = 2 × BW).

The oversampling ratio (OSR) is a key parameter of any Σ-Δ

ADC and is defined as follows:

OSR = FADC/(2 × BW)

(1)

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