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TNETX3150 数据表(PDF) 102 Page - Texas Instruments

部件名 TNETX3150
功能描述  ThunderSWITCHE 15-PORT 10-/100-MBIT/S ETHERNETE SWITCH
PDF  113 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETX3150 数据表(HTML) 102 Page - Texas Instruments

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TNETX3150/TNETX3150A
ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH
SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997
102
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
operating characteristics over recommended operating conditions (see Figure 43)
EEPROM interface
NO
PARAMETER
TNETX3150
TNETX3150A
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
fclock (ECLK)
Clock frequency, ECLK
98
98
kHz
1
td (ECLKH–EDIOL)
Delay time, from ECLK
↑ to EDIO↓ (see Note 13)
5
5
µs
2
td (EDIOL–ECLKL)
Delay time, from EDIO
↓ to ECLK↓ (see Note 13)
5
5
µs
3
td (ECLKL–EDIOX)
Delay time, from ECLK
↓ to EDIO changing (see Note 14)
0
0
µs
4
td (EDIOV–ECLKH)
Delay time, from EDIO valid output to ECLK
↑
0
0
µs
5
td (ECLKL–EDIOV)
Delay time, from ECLK
↓ to EDIO valid
0
0
µs
6
td (ECLKL–EDIOX)
Delay time, from ECLK
↓ to EDIO changing (see Note 15)
0
0
µs
7
td (ECLKH–EDIOX)
Delay time, from ECLK
↑ to EDIO invalid
5
5
µs
8
td (EDIOV–ECLKH)
Delay time, from EDIO valid input to ECLK
↑
10
10
µs
NOTES: 13. This is a start condition delay time during ECLK high.
14. This is a changing-data condition delay time for output EDIO.
15. This is a changing-data condition delay time for input EDIO.
7
ECLK
(output)
EDIO
(output)
EDIO
(input)
1
2
5
6
3
4
8
VALID
VALID
VALID
VALID
Figure 43. EEPROM Interface Timing



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