| 数据搜索系统,热门电子元器件搜索 |
|
TNETX3150 数据表(PDF) 104 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TNETX3150 数据表(HTML) 104 Page - Texas Instruments |
|
104 / 113 page ![]() TNETX3150/TNETX3150A ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997 104 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating conditions (see Figure 45) MII transmit 100/200 Mbit/s (XX = ports 00–02) NO PARAMETER TNETX3150 TNETX3150A UNIT NO. PARAMETER MIN MAX MIN MAX UNIT 1 td(MXXTXD)1 Delay time, from MXXTCLK ↑ to MXXTXD3–MXXTXD0 valid 5 25 2.5 25 ns 1† td(MXXTXD)2 Delay time, from MXXTCLK ↑ to MXXTXD7–MXXTXD0 valid 5 25 2.5 25 ns 1 td(MXXTXEN) Delay time, from MXXTCLK ↑ to MXXTXEN valid 5 25 2.5 25 ns 1 td(MXXTXER) Delay time, from MXXTCLK ↑ to MXXTXER valid 5 25 2.5 25 ns † Also applies to the uplink (port 00) when operating in the 200 Mbit/s mode, except that MXXRXD3–MXXRXD0 is replaced with MXXRXD7–MXXRXD0 and MXXRXDVX is used. MXXTXD3–MXXTXD0 is driven by the reconciliation sublayer synchronous to the MXXTCLK. MXXTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MXXTCLK rising edge. MXXTXER is driven synchronous to the rising edge of MXXTCLK (XX = ports 00–02). MXXTCLK (input) MXXTXD7–MXXTXD0 MXXTXD3–MXXTXD0 MXXTXEN MXXTXER (outputs) 1 Figure 45. Ports (00–02) Transmit Interface Timing |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |