TNETV1644ZDU6 datasheet(110/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 3-20. PINMUX1 Register Descriptions (continued)

Bit

Field Name

Description

Pins Controlled

Host Block:

See list of 27 pins in HOSTBK bit field

description

PCI Data Block:

AD26

AD28

AD30

GPIO Block:

AD0/GP[0]

AD1/GP[1]

PCI Enable.

AD2/GP[2]

AD4/GP[3]

The PINMUX1.PCIEN reflects the state of the PCIEN pin. PINMUX1.PCIEN is

read only and cannot be modified by software. For proper device

EMIFA/VPSS Sub-Block 0*:

operation, the user must hold the desired setting at the PCIEN pin

CI7(CCD15)/EM_A[13]/AD25/EM_D[0]/GP[51]

throughout device operation.

CI6(CCD14)/EM_A[14]/AD27/EM_D[1]/GP[50]

CI5(CCD13)/EM_A[15]/AD29/EM_D[2]/GP[49]

PCIEN = 0: No PCI supported. Internal pullup/pulldown (IPU/IPD) on these pins

CI4(CCD12)/EM_A[16]/PGNT/EM_D[3]/GP[48]

are enabled.

CI3(CCD11)/EM_A[17]/AD31/EM_D[4]/GP[47]

For PCI multiplexed pins in the GPIO Block, when PCIEN = 0, the pins function

CI2(CCD10)/EM_A[18]/PRST/EM_D[5]/GP[46]

as GPIO (GP[3:0]).

CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]

For PCI multiplexed pins in the Host Block, refer to PINMUX1.HOSTBK field for

CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]

PCIEN

the actual pin functions.

EMIFA/VPSS Sub-Block 3*:

For PCI multiplexed pins in the EMIFA/VPSS Block, refer to PINMUX0.AEM,

EM_A[12]/PCBE3/GP[89]

AEAW, CI76SEL, CI54SEL, CI32SEL, and CI10SEL fields for the actual pin

EM_A[11]/AD24/GP[90]

functions.

EM_A[10]/AD23/GP[91]

For PCI pins in the PCI Data Block, when PCIEN = 0, the pins have no function

EM_A[9]/PIDSEL/GP[92]

and should be left unconnected.

EM_A[8]/AD21/GP[93]

PCIEN = 1: PCI supported. Internal pullup/pulldown (IPU/IPD) on all PCI pins

EM_A[7]/AD22/GP[94]

are disabled.

EM_A[6]/AD20/GP[95]

EM_A[5]/AD19/GP[96]

All pins function as PCI pins.

Applicable only for PINMUX0.AEM = 000b or 101b.

The pin mux for the EMIFA/VPSS Sub-Block 0

and EMIFA/VPSS Sub-Block 3 pins are

controlled by a combination of PCIEN and other

PINMUX0/1 fields, including HOSTBK, AEM,

AEAW, CI76SEL, CI54SEL, CI32SEL, and

CI10SEL. See Section 3.7.3.13.7, EMIFA/VPSS

Block Pin-By-Pin Multiplexing Summary, for the

full set of valid configurations of EMIFA/VPSS

Block pins.

For the full set of valid configurations of Host

Block pins, see Section 3.7.3.3, Host Block

Muxing.

Device Configurations

110

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