 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TNETV1644ZDU6 数据表(PDF) 111 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TNETV1644ZDU6 数据表(HTML) 111 Page - Texas Instruments |
|
|
111 / 306 page  3.7.3 Pin Multiplexing Details 3.7.3.1 Multiplexed Pins on DM6437 TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 This section discusses how to program each Pin Mux Block to select the desired peripheral functions. The following steps can be used to determine pin muxing suitable for the application: 1. Understand the major configuration choices available for the specific application. a. Device Major Configuration Choices: Figure 3-11 shown in Section 3.7, Multiplexed Pin Configurations, provides a high-level view of the device pin muxing and can be used to determine the possible mix of peripheral options for a specific application. b. EMIFA/VPSS Block Major Configuration Choices: The EMIFA/VPSS block features extensive pin multiplexing to accommodate a variety of applications. In addition to Figure 3-11, Section 3.7.3.13, EMIFA/VPSS Block Muxing, provides more details on the Major Configuration choices for this block. 2. See Section 3.7.3.1, Multiplexed Pins on DM6437, for a summary of all the multiplexed pins on this device and the pin mux group they belong to. 3. Refer to the individual pin mux sections (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.13, EMIFA/VPSS Block Muxing) for pin muxing details for a specific pin mux block. a. For peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that peripheral in all relevant pin mux blocks. For more details, see Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks. For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2. Table 3-21 summarizes all of the multiplexed pins on DM6437, the pin mux group for each pin, and the PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.13, EMIFA/VPSS Block Muxing). For a description of the PINMUX register fields, see Section 3.7.2. Table 3-21. Multiplexed Pins on DM6437 SIGNAL PINMUX DESCRIPTION ZWT ZDU NAME PINMUX GROUP CONTROLLED BY PINMUX BIT FIELDS NO. NO. PCLK/GP[54] A14 A18 EMIFA/VPSS Sub-Block 0 CCDCSEL VD/GP[53] A13 A17 EMIFA/VPSS Sub-Block 0 HVDSEL HD/GP[52] A15 A19 EMIFA/VPSS Sub-Block 0 HVDSEL CI7(CCD15)/EM_A[13]/AD25/ B10 A12 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI76SEL EM_D[0]/GP[51] CI6(CCD14)/EM_A[14]/AD27/ A10 A13 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI76SEL EM_D[1]/GP[50] CI5(CCD13)/EM_A[15]/AD29/ B11 C13 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI54SEL EM_D[2]/GP[49] CI4(CCD12)/EM_A[16]/PGNT/ C11 B13 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI54SEL EM_D[3]/GP[48] CI3(CCD11)/EM_A[17]/AD31/ A11 B14 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI32SEL EM_D[4]/GP[47] CI2(CCD10)/EM_A[18]/PRST/ D11 A14 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI32SEL EM_D[5]/GP[46] CI1(CCD9)/EM_A[19]/PREQ/ B12 C14 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI10SEL EM_D[6]/GP[45] CI0(CCD8)/EM_A[20]/PINTA/ C12 C15 EMIFA/VPSS Sub-Block 0 PCIEN, AEM, AEAW, CI10SEL EM_D[7]/GP[44] YI7(CCD7)/GP[43] A12 A15 EMIFA/VPSS Sub-Block 0 CCDCSEL YI6(CCD6)/GP[42] B13 B15 EMIFA/VPSS Sub-Block 0 CCDCSEL YI5(CCD5)/GP[41] C13 B16 EMIFA/VPSS Sub-Block 0 CCDCSEL Submit Documentation Feedback Device Configurations 111 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
