5222-DS02-R datasheet(27/76 Pages) BOARDCOM

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Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

Power Saving Modes

Page 15

The Interrupt register (1Ah) also contains several bits to control different facets of the interrupt function. If the interrupt enable

bit is set to 0, no status bits are set and no interrupts are generated. If the interrupt enable bit is set to 1, the following

conditions apply:

•

If mask status bits (bits 9,10,11) are set to 0 and the interrupt mask (bit 8) is set to 0, status bits and interrupts are

available.

•

If mask status bits (bits 9,10,11) are set to 0 and the interrupt mask (bit 8) is set to 1, status bits are set but no interrupts

generated.

•

If any mask status bit is set to 1 and the interrupt mask is set to 0, that status bit is not set and no hardware interrupt of

that type is generated.

•

If any mask status bit is set to 1 and the interrupt mask is set to 1, that status bit is not set and no interrupt of any kind is

generated.

POWER SAVING MODES

Several power saving modes are implemented in the BCM5222. Table 5 shows low power modes available in the BCM5222.

Low power modes can be achieved either by hardware pin or MII register programming. The table shows both hardware pin

and software bits that determine the low power modes and whether the BCM5222 keeps the clocks active. The BCM5222

requires a hard reset to return to normal mode from a low power mode if the clocks are not running. Allow at least 2 ms

before resuming normal operation with the BCM5222 after the device is set to run in normal mode from a low power mode.

Table 5: Low Power Modes

Hardware Settings

Software Setting

Chip Operation

LOW_PWR

RESET

FORCE

IDDQ

LOW_PWR

MODE

ENABLE

CLOCK

CLOCKS

AUTO

MDIX

COMMENT

OFF

Reset State.

Avail

Normal operation without any power saving

modes active.

OFF

Force Iddq register serves as a software

induced power-down mode.

OFF

Low Power Mode without CLK functioning,

induced through hardware.

Avail

Low Power Mode with CLK functioning, induced

through hardware.

OFF

Low Power Mode without CLK functioning,

induced through software.

Avail

Low Power Mode with CLK functioning, induced

through software.

LOW_PWR: Pin 27 (Active high)

RESET: Pin 68 (Active Low)

Force Iddq: Bit 0 of Shadow register 1Ah (0

−Normal Op. 1−Power down)

Low Power Mode: Bit 1 of Shadow register 1Ah(0

−Normal Op. 1−Low Power Mode)

Enable Clock: Bit 2 of Shadow register 1Ah(0

−Disabled in LP mode 1−Enabled)

Clock Operation: If clock is off, additional power is saved.

Auto-MDIX Operation: Only available if device has clock running.

X=1/0 or Don’t Care

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