5222-DS02-R datasheet(59/76 Pages) BOARDCOM

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Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

Timing and AC Characteristics

Page 47

Section 6: Timing and AC Characteristics

The timing information contained in this section applies to the BCM5222.

All MII Interface pins comply with IEEE 802.3u timing specifications (see Reconciliation Sublayer and Media Independent

Interface in IEEE 802.3u timing specifications). All digital output timing specified at CL = 30 pF.

Output rise/fall times measured between 10% and 90% of the output signal swing. Input rise/fall times measured between

VIL max. and VIH min. Output signal transitions referenced to the midpoint of the output signal swing. Input signal transitions

referenced to the midpoint between VIL max. and VIH min. See Table 34and Table 35 for the timing parameters. See

Figure 4 for an illustration of clock and reset timing.

Figure 4: Clock and Reset Timing

Table 34: Clock Timing

Parameter

Symbol

Min

Typical

Max

Unit

XTALI Cycle Time

CK_CYCL

39.998

40.002

XTALI High/Low Time

CK_HI

CK_LO

XTALI Rise/Fall Time

CK_EDGE

Table 35: Reset Timing

Parameter

Symbol

Min

Typical

Max

Unit

Reset Pulse Length with stable XTALI Input

RESET_LEN

400

Activity after end of Hardware Reset

RESET_WAIT

100

µs

RESET Rise/Fall Time

RESET_EDG

XTALI

RESET

Normal PHY

RESET_LEN

RESET_WAIT

CK_HI

CK_CYCLE

CK_EDGE

CK_LO

CK_EDGE

activity begins here

RESET_EDGE

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