5222-DS02-R datasheet(53/76 Pages) BOARDCOM

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Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

Auxiliary Multiple PHY Register

Page 41

HCD BITS

Bits 15:11 of the Auxiliary Multiple PHY register are 5 read-only bits that report the Highest Common Denominator (HCD)

result of the auto-negotiation process. Immediately upon entering the link pass state after each reset or restart auto-

negotiation, only 1 of these 5 bits is 1. The link pass state is identified by a 1 in bit 6 or 7 of this register. The HCD bits are

reset to 0 every time auto-negotiation is restarted or the BCM5222 is reset. For their intended application, these bits uniquely

identify the HCD only after the first link pass after reset or restart of auto-negotiation. On later Link Fault and subsequent re-

negotiations, if the ability of the link partner is different, more than 1 of the above bits can be active.

RESTART AUTO-NEGOTIATION

This self-clearing bit allows the auto-negotiation process to be restarted, regardless of the current status of the state

machine. For this bit to work, auto-negotiation must be enabled. Writing a 1 to this bit restarts auto-negotiation. Since the bit

is self-clearing, it always returns a 0 when read. The operation of this bit is identical to bit 9 of the Control register.

Auto-Negotiation Complete

This read-only bit returns a 1 after the auto-negotiation process has been completed. It remains 1 until the auto-negotiation

process is restarted, a Link Fault occurs, or the chip is reset. If auto-negotiation is disabled or the process is still in progress,

the bit returns a 0.

ACKNOWLEDGE COMPLETE

This read-only bit returns a 1 after the acknowledgment exchange portion of the auto-negotiation process has been

completed and the Arbitrator state machine has exited the Complete Acknowledge state. It remains this value until the auto-

negotiation process is restarted, a Link Fault occurs, auto-negotiation is disabled, or the BCM5222 is reset.

ACKNOWLEDGE DETECTED

This read-only bit is set to 1 when the arbitrator state machine exits the acknowledged detect state. It remains high until the

auto-negotiation process is restarted, or the BCM5222 is reset.

Acknowledge Detected

1 = Auto-negotiation acknowledge detected

Ability Detect

1 = Auto-negotiation waiting for LP ability

Super Isolate

R/W

1 = Super isolate mode

0 = Normal operation

Reserved

Ignore when read

10BASE-T Serial Mode

R/W

1 = Enable 10BASE-T serial mode

0 = Disable 10BASE-T serial mode

Reserved

R/W

Write as 0, Ignore when read

Table 25: Auxiliary Multiple PHY Register (Address 30d, 1Eh)

Bit

Name

R/W

Description

Default

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

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