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5222-DS02-R 数据表(PDF) 31 Page - Broadcom Corporation. |
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5222-DS02-R 数据表(HTML) 31 Page - Broadcom Corporation. |
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31 / 76 page ![]() Preliminary Data Sheet BCM5222 7/20/04 Broadcom Corporation Document 5222-DS02-405-R MII Control Register Page 19 POWER DOWN The power modes of the BCM5222 are not accessible by this MII register bit. Use Shadow register control instead. ISOLATE The PHY can be isolated from its Media Independent Interface by writing a 1 to bit 10 of the Control register. All MII outputs are tri-stated and all MII inputs are ignored. Because the MII management interface is still active, the isolate mode can be cleared by writing a 0 to bit 10 of the Control register, or by resetting the chip. When this bit is read, it returns a 1 when the chip is in isolate mode; otherwise it returns a 0. RESTART AUTO-NEGOTIATION Bit 9 of the Control register is a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of the current status of the auto-negotiation state machine. For this bit to have an effect, auto-negotiation must be enabled. Writing a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect. Because the bit is self-clearing after only a few cycles, it always returns a 0 when read. The operation of this bit is identical to bit 8 of the Auxiliary Multiple PHY register (1Eh). Duplex Mode This bit is logically or'd with the hardware pin, FDX, whenever Auto-negotiation is disabled. COLLISION TEST Test the COL pin by activating the collision test mode. While in this mode, asserting TXEN causes the COL output to go high within 512 bit times. Deasserting TXEN causes the COL output to go low within 4 bit times. Writing a 1 to bit 7 of the Control register enables the collision test mode. Writing a 0 to this bit or resetting the chip disables the collision test mode. When this bit is read, it returns a 1 when the collision test mode has been enabled; otherwise it returns a 0. This bit should only be set while in loopback test mode. RESERVED BITS All reserved MII register bits must be written as 0 at all times. Ignore the BCM5222 output when these bits are read. |
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