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5222-DS02-R 数据表(PDF) 21 Page - Broadcom Corporation. |
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5222-DS02-R 数据表(HTML) 21 Page - Broadcom Corporation. |
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21 / 76 page ![]() Preliminary Data Sheet BCM5222 7/20/04 Broadcom Corporation Document 5222-DS02-405-R Hardware Signal Definitions Page 9 E10 65 TMS/TXER{1} IPD Test Mode Select. This pin becomes TMS if TRST is high. Single control input to the JTAG TAP controller is used to traverse the test-logic state machine. Sampled on the rising edge of TCK. F9 64 TDO/PAUSE{1} O3S Test Data Output. This pin becomes TDO if TRST is high. Serial data output from the JTAG TAP controller. Updated on the falling edge of TCK. POWER B8, C4 99, 82 DVDD PWR Digital VDD (1.8V). Connect these pins to decoupling capacitors as shown in Figure 17 on page 60. J5 41 AVDD PWR Analog VDD (1.8V). Connect this pin to decoupling capacitors as shown in Figure 17 on page 60. B3, C8, D1, E8, G1, H10 1, 11, 22, 56, 70, 80 OVDD PWR 3.3V Digital Periphery (Output Buffer) VDD supply. B6, B4, B9 100, 90, 81 DGND GND Digital Ground. G5, J6, H5, H6 39, 40, 42, 43 AGND GND Analog Ground. J2 28 BIASVDD PWR BIAS VDD (3.3V). Connect this pin to decoupling capacitors as shown in Figure 17 on page 60. J3 30 BIASGND GND Bias Ground. Connect this pin to AGND. H7, H1, D2, E9 12, 23, 55, 69 OGND GND Output Buffer Ground. Digital Periphery (Output Buffer) ground. J4 34 PLLAGND GND PLL Analog Ground. Phase Locked Loop ground. K1 31 PLLAVDD PWR PLL Analog VDD (1.8V). 1.8V, Phase Locked Loop VDD Core. Connect this pin to decoupling capacitors as shown in Figure 17 on page 60. NO CONNECTS J8, J9 G3, F10 26, 48, 49, 61 NC NC No Connection. Leave these pins floating. Table 3: Pin Descriptions (Cont.) BGA MQFP Pin Label Type Description [MSB:LSB]; OVERLINE = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD = open-drain output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground |
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