5222-DS02-R datasheet(41/76 Pages) BOARDCOM

41 / 76 page

Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

100BASE-TX Auxiliary Control Register

Page 29

TRANSMIT DISABLE

The transmitter can be disabled by writing a 1 to bit 13 of MII register 10h. The transmitter output (TD±) is forced into a high

impedance state.

BYPASS 4B5B ENCODER/DECODER

The 4B5B encoder and decoder can be bypassed by writing a 1 to bit 10 of MII register 10h. The transmitter sends 5B codes

from the TXER and TXD[3:0] pins directly to the scrambler. TXEN must be active and frame encapsulation (insertion of J/K

and T/R codes) is not performed. The receiver places descrambled and aligned 5B codes onto the RXER and RXD[3:0] pins.

CRS can be asserted when a valid frame is received.

BYPASS SCRAMBLER/DESCRAMBLER

The stream cipher function can be disabled by writing a 1 to bit 9 of MII register 10h. The stream cipher function is re-enabled

by writing a 0 to this bit.

BYPASS NRZI ENCODER/DECODER

The NRZI encoder and decoder can be bypassed by writing a 1 to bit 8 of MII register 10h, causing 3-level NRZ data to be

transmitted and received on the cable. Normal operation (3-level NRZI encoding and decoding) can be re-enabled by writing

a 0 to this bit.

BYPASS RECEIVE SYMBOL ALIGNMENT

Receive symbol alignment can be bypassed by writing a 1 to bit 7 of MII register 10h. When used in conjunction with the

bypass 4B5B encoder/decoder bit, unaligned 5B codes are placed directly on the RXER and RXD[3:0] pins.

BASELINE WANDER CORRECTION DISABLE

The baseline wander correction circuit can be disabled by writing a 1 to bit 6 of MII register 10h. The BCM5222 corrects for

baseline wander on the receive data signal when this bit is cleared.

RESERVED BITS

The reserved bits of the 100BASE-TX Auxiliary Control register must be written as 0 at all times. Ignore the BCM5222

outputs when these bits are read.

5222-DS02-R 数据表(PDF) 41 Page - Broadcom Corporation.