5222-DS02-R datasheet(54/76 Pages) BOARDCOM

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BCM5222

Preliminary Data Sheet

7/20/04

Broadcom Corporation

Page 42

Broadcom Test Register

Document 5222-DS02-405-R

ABILITY DETECT

This read-only bit returns a 1 when the auto-negotiation state machine is in the Ability Detect state. It enters this state a

specified time period after the auto-negotiation process begins, and exits after the first FLP burst or link pulses are detected

from the link partner. This bit returns a 0 any time the auto-negotiation state machine is not in the Ability Detect state.

SUPER ISOLATE

Writing a 1 to this bit places the BCM5222 into the Super Isolate mode. Similar to the Isolate mode, all MII inputs are ignored,

and all MII outputs are tri-stated. Additionally, all link pulses are suppressed. This allows the BCM5222 to coexist with

another PHY on the same adapter card, with only one being activated at any time.

10BASE-T SERIAL MODE

Writing a 1 to bit 1 of the Auxiliary Mode register enables the 10BASE-T Serial mode. In the normal 10BASE-T mode of

operation, as defined by the MII standard, transmit and receive data packets traverse the TXD[3:0] and RXD[3:0] busses at

a rate of 2.5 MHz. In the special 10BASE-T Serial mode, data packets traverse to the MAC layer across only TXD0 and

RXD0 at a rate of 10 MHz. Serial operation is not available in 100BASE-TX mode.

BROADCOM TEST REGISTER

SHADOW REGISTER ENABLE

Writing a 1 to bit 7 of register 1Fh allows R/W access to the Shadow registers.

Table 26: Broadcom Test (Address 31d, 1Fh)

BIt

Name

R/W

Description

Default

15:8

Reserved

Ignore when read

00h

Shadow Register Enable

R/W

1 = Enable Shadow registers

0 = Disable Shadow registers

Reserved

Ignore when read

Reserved

R/W

Write as 0, Ignore when read

4:0

Reserved

R/W

Write as 0Bh, Ignore when read

0Bh

Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after

read operation. Use default values of reserved bit(s) when writing to reserved bit(s).

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