5222-DS02-R datasheet(29/76 Pages) BOARDCOM

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Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

MII Control Register

Page 17

TURNAROUND (TA)

The next two bit times are used to avoid contention on the MDIO pin when a read operation is performed. For a write

operation, 10 must be sent to the chip during these two bit times. For a read operation, the MDIO pin must be placed into

high-impedance during these two bit times. The chip drives the MDIO pin to 0 during the second bit time.

DATA

The last 16 bits of the frame are the actual data bits. For a write operation, these bits are sent to the BCM5222. For a read

operation, these bits are driven by the BCM5222. In either case, the MSB is transmitted first.

When writing to the BCM5222, the data field bits must be stable 10 ns before the rising-edge of MDC, and must be held valid

for 10 ns after the rising edge of MDC. When reading from the BCM5222, the data field bits are valid after the rising edge of

MDC until the next rising edge of MDC.

IDLE

A high-impedance state of the MDIO line. All drivers are disabled and the PHY’s pull-up resistor pulls the line high. At least

one or more clocked idle states are required between frames. Following are two examples of MII write and read instructions.

To put a chip with PHY address 00001 into loopback mode, the following MII write instruction must be issued:

1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1...

To determine whether a PHY is in the link pass state, the following MII read instruction must be issued:

1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 ZZ ZZZZ ZZZZ ZZZZ ZZZZ 1...

For the MII read operation, the BCM5222 drives the MDIO line during the TA and Data fields (the last 17 bit times). A final

65th clock pulse must be sent to close the transaction and cause a write operation.

MII CONTROL REGISTER

The MII Control register bit descriptions are shown in Table 7.

Table 7: MII Control Register (Address 00000b, 0d, 00h)

Bit

Name

R/W

Description

Default

Reset

R/W

(SC)

1 = PHY reset

0 = Normal operation

Loopback

R/W

1 = Loopback mode

0 = Normal operation

Forced Speed Selection

R/W

1 = 100 Mbps

0 = 10 Mbps

Auto-Negotiation Enable

R/W

1 = Auto-negotiation enable

0 = Auto-negotiation disable

Power Down

0 = Normal operation

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