5222-DS02-R datasheet(18/76 Pages) BOARDCOM

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BCM5222

Preliminary Data Sheet

7/20/04

Broadcom Corporation

Page 6

Hardware Signal Definitions

Document 5222-DS02-405-R

Section 2: Hardware Signal Definitions

Table 3 provides the pin descriptions for the BCM5222 BGA and MQFP packages.

Table 3: Pin Descriptions

BGA

MQFP

Pin Label

Type

Description

MEDIA CONNECTIONS

K5, K6

K4, K7

38, 44

37, 45

RD+{2}, RD+{1}

−{2}, RD-{1}

I/O

Receive Pair. Differential data from the media is received on

the RD

± signal pair. This pair will function as TX± in the MDIX

configuration.

K2, K9

K3, K8

35, 47

36, 46

TD+{2}, TD+{1}

−{2}, TD-{1}

I/O

Transmit Pair. Differential data is transmitted to the media on

the TD

± signal pair. This pair will function as RX± in the MDIX

configuration.

CLOCK

H3, H4

XTALI

XTALO

I/O

Crystal Input, Output. A continuous 25 MHz reference clock

must be supplied to the BCM5222 by connecting a 25 MHz

crystal between these two pins or by driving XTALI with an

external 25 MHz clock. When using a crystal, connect a

loading capacitor from each pin to ground. When using an

oscillator, leave XTALO unconnected.

MII INTERFACE

A2, C7

97, 84

TXC{2}, TXC{1}

O3S

Transmit Clock. 25-MHz output in 100BASE-TX mode and

2.5 MHz in 10BASE-T MII mode. 10-MHz output in 10BASE-

T serial mode. This clock is a continuously driven output,

generated from the XTALI input.

D5, A8

A3, B7

D6, A7

A4, C6

96, 85

95, 86

94, 87

93, 88

TXD3{2}, TXD3{1}

TXD2{2}, TXD2{1}

TXD1{2}, TXD1{1}

TXD0{2}, TXD0{1}

IPD

MII Transmit Data Input. Nibble-wide transmit data stream is

input on these pins synchronous with TXC. TXD3 is the most

significant bit. Only TXD0 is used in 10BASE-T serial mode.

C5, A9

98, 83

TXEN{2}, TXEN{1}

IPD

MII Transmit Enable. Active high. Indicates that the data

nibble on TXD[3:0] is valid.

G8, E10

62, 65

TDI/TXER{2}, TMS/

TXER{1}

IPD

MII Transmit Error. An active high input is asserted when a

transmit error condition is requested by the MAC.

C2, D9

8, 73

RXC{2}, RXC{1}

O3S

MII Receive Clock. 25-MHz output in 100BASE-TX MII mode

and 2.5-MHz output in 10BASE-T MII mode. 10-MHz output

in 10BASE-T serial mode. This clock is recovered from the

incoming data on the cable inputs. RXC is a continuously

running output clock resynchronized at the start of each

incoming packet. This synchronization may result in an

elongated period during one cycle while RXDV is low.

A1, D7

B2, A10

C3, C9

B1, D8

2, 79

3, 78

4, 77

5, 76

RXD3{2}, RXD3{1}

RXD2{2}, RXD2{1}

RXD1{2}, RXD1{1}

RXD0{2}, RXD0{1}

O3S

MII Receive Data Outputs. Nibble-wide receive data stream

is driven out on these pins synchronous with RXC. RXD3 is

the most significant bit. Only RXD0 is used in 10BASE-T

serial mode.

D4, B10

6, 75

RXDV{2}, RXDV{1}

O3S

MII Receive Data Valid. Active high. Indicates that a receive

frame is in progress, and that the data stream present on the

RXD output pins is valid.

[MSB:LSB]; OVERLINE = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD

= open-drain output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground

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