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5222-DS02-R 数据表(PDF) 57 Page - Broadcom Corporation. |
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5222-DS02-R 数据表(HTML) 57 Page - Broadcom Corporation. |
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57 / 76 page ![]() Preliminary Data Sheet BCM5222 7/20/04 Broadcom Corporation Document 5222-DS02-405-R Auxiliary Status 3 Register (Shadow Register) Page 45 AUXILIARY STATUS 3 REGISTER (SHADOW REGISTER) NOISE [7:0] The BCM5222 provides the current mean squared error value for noise when a valid link is established. FIFO CONSUMPTION [3:0] The BCM5222 indicates the number of nibbles of FIFO currently used. AUXILIARY MODE 3 REGISTER (SHADOW REGISTER) FIFO SIZE SELECT [3:0] The BCM5222 indicates the current selection of receive FIFO size using bit 3 through 0 as shown in Table 32. Table 30: Auxiliary Status 3 Register (Shadow Register 28d, 1Ch) BIt Name R/W Description Default 15:8 Noise [7:0] R/O Current mean square error value, valid only if link is established 00h 7:4 Reserved R/W Write as 0, ignore when read 0h 3:0 FIFO Consumption [3:0] R/O Currently utilized number of nibbles in the receive FIFO 0000 Note: MII Shadow register bank 1 is accessed by setting MII register 1Fh bit 7 to a 1 Table 31: Auxiliary Mode 3 Register (Shadow Register 29d, 1Dh) BIt Name R/W Description Default 15:4 Reserved R/W Write as 00h, ignore when read 000h 3:0 FIFO Size Select [3:0] R/W Currently selected receive FIFO Size 4h Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after read operation. Use default values of reserved bit(s) when writing to reserved bit(s). MII Shadow register bank 1 is accessed by setting MII register 1Fh bit 7 to a 1. Table 32: Current Receive FIFO Size FIFO Size Select [3:0] Receive FIFO Size in Use (# of Bits) 0001 16 0010 20 0011 24 0100 28 |
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