5222-DS02-R datasheet(19/76 Pages) BOARDCOM

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Preliminary Data Sheet

BCM5222

7/20/04

Broadcom Corporation

Document 5222-DS02-405-R

Hardware Signal Definitions

Page 7

C1, E6

7, 74

RXER{2}, RXER{1}

O3S

MII Receive Error Detected. Active high. Indicates that an

error is occurring during a receive frame.

E5, C10

9, 72

CRS{2}, CRS{1}

O3S

MII Carrier Sense. Active high. Indicates traffic on link. In

100BASE-TX mode, CRS is asserted when a non-idle

condition is detected in the receive data stream and

deasserted when idle or a valid end of stream delimiter is

detected. In 10BASE-T mode, CRS is asserted when a valid

preamble is detected and deasserted when end-of-file or an

idle condition is detected. CRS is also asserted during

transmission of packets except in full-duplex modes. CRS is

an asynchronous output signal.

D3, E7

10, 71

COL{2}, COL{1}

O3S

Collision Detect. In half-duplex modes, active high output

indicates that a collision has occurred. In full-duplex mode,

COL remains low. COL is an asynchronous output signal.

MDIO

I/OPU Management Data I/O. This serial input/output bit is used to

read from and write to the MII registers of each of the PHYs.

The data value on the MDIO pin is valid and latched on the

rising edge of MDC.

MDC

IPD

Management Data Clock. The MDC clock input must be

provided to allow MII management functions.

Clock frequencies up to 25 MHz are supported.

MODE

D10

RESET

IPU

Reset. Active Low. Resets the BCM5222. Also used to

enable Power Off and Low Power modes.

E1, E4

13, 14

PHYAD0, PHYAD1,

IPU

PHY Address Selects PHYAD[1:0]. These inputs set the two

least significant bits of the MII management PHY address for

PHY 1. PHY 2 address will be one greater than the PHY 1

address.These pins are sampled only during power-on reset.

E3, E2,

15, 16,

PHYAD2, PHYAD3,

PHYAD4

IPD

PHY Address Selects PHYAD[4:2]. These inputs set the

three most significant bits of the MII management PHY

address for PHY 1. PHY 2 address will be one greater than

the PHY 1 address.These pins are sampled only during

power-on reset.

51,

PAUSE{2},

TDO/PAUSE{1}

OPD

PAUSE. Status of the link partner’s PAUSE bit, bit 10d of MII

Link Partner Ability register 05d.

TCK/FDX

IPU

Full-Duplex Mode. When auto-negotiation is disabled, the

FDX pin is logically ORed with register 00, bit 8 to select full-

duplex (1) or half-duplex (0) operation. (This pin becomes

TCK if TRST pin is high.) When auto-negotiation is enabled,

this pin is ignored.

LOW_PWR

IPD

Low Power Mode Enable. Active high input places the

BCM5222 into Low Power operation with the chip deactivated

except for the crystal oscillator if bit 2 of Shadow register 1Ah

is set to the non-default value of 1. When asserted with

RESET pulled low, the entire chip is deactivated (Power Off

mode).

Table 3: Pin Descriptions (Cont.)

BGA

MQFP

Pin Label

Type

Description

[MSB:LSB]; OVERLINE = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD

= open-drain output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground

5222-DS02-R 数据表(PDF) 19 Page - Broadcom Corporation.

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