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5222-DS02-R 数据表(PDF) 35 Page - Broadcom Corporation. |
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5222-DS02-R 数据表(HTML) 35 Page - Broadcom Corporation. |
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35 / 76 page ![]() Preliminary Data Sheet BCM5222 7/20/04 Broadcom Corporation Document 5222-DS02-405-R Auto-Negotiation Advertisement Register Page 23 NEXT PAGE Writing a 1 to bit 15 of the Advertisement register enables the next page functioning. Writing a 0 to this bit or resetting the chip clears the next page enable bit. This bit returns the value last written to it, or else 0 if no write has been completed since the last chip reset. RESERVED BITS Ignore output when read. REMOTE FAULT Writing a 1 to bit 13 of the Advertisement register causes a remote fault indicator to be sent to the link partner during auto- negotiation. Writing a 0 to this bit or resetting the chip clears the remote fault transmission bit. This bit returns the value last written to it, or else 0 if no write has been completed since the last chip reset. RESERVED BITS Ignore output when read. PAUSE Pause operation for full-duplex links. The use of this bit is independent of the negotiated data rate, medium, or link technology. The setting of this bit indicates the availability of additional DTE capability when full-duplex operation is in use. This bit is used by one MAC to communicate pause capability to its link partner and has no effect on PHY operation. ADVERTISEMENT BITS Use bits 9:5 of the Advertisement register to customize the ability information transmitted to the link partner. The default value for each bit reflects the abilities of the BCM5222. By writing a 1 to any of the bits, the corresponding ability can be transmitted to the link partner. Writing a 0 to any bit causes the corresponding ability to be suppressed from transmission. Resetting the chip restores the default bit values. Reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. SELECTOR FIELD Bits 4:0 of the Advertisement register contain the value 00001, indicating that the chip belongs to the 802.3 class of PHY transceivers. 5 Advertise 10BASE-T R/W 1 = Advertise 10BASE-T 1 4:0 Advertise Selector Field R/W Indicates 802.3 00001 Table 10: Auto-Negotiation Advertisement Register (Address 04d, 04h) (Cont.) Bit Name R/W Description Default Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after read operation. Use default values of reserved bit(s) when writing to reserved bit(s). |
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