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5222-DS02-R 数据表(PDF) 34 Page - Broadcom Corporation. |
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5222-DS02-R 数据表(HTML) 34 Page - Broadcom Corporation. |
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34 / 76 page ![]() BCM5222 Preliminary Data Sheet 7/20/04 Broadcom Corporation Page 22 PHY Identifier Registers Document 5222-DS02-405-R PHY IDENTIFIER REGISTERS The physical indentifier registers bit descriptions are shown in Table 9. Broadcom Corporation has been issued an Organizationally Unique Identifier (OUI) by the IEEE. It is a 24-bit number, 00- 10-18, expressed as hex values. That number, along with the Broadcom Model Number for the BCM5222 part, 32h, and Broadcom Revision number (n), is placed into two MII Registers. The translation from OUI, Model Number and Revision Number to PHY Identifier register occurs as follows: • PHYID HIGH [15:0] = OUI[21:6] • PHY LOW [15:0] = OUI[5:0] + MODEL[5:0] + REV[3:0] The 2 most significant bits of the OUI are not represented (OUI[23:22]). Table 9 shows the result of concatenating these values to form MII Identifier Registers PHYID HIGH and PHYID LOW. AUTO-NEGOTIATION ADVERTISEMENT REGISTER Table 9: PHY Indentifier Registers (Addresses 00010 and 00011b, 02 and 03b, 02 and 03h) Bit Name R/W Description Value 15:0 MII Address 02h RO PHYID HIGH 0040h 15:0 MII Address 03h RO PHYID LOW 632n (Hex) Note: The revision number (n) changes with each silicon revision. Table 10: Auto-Negotiation Advertisement Register (Address 04d, 04h) Bit Name R/W Description Default 15 Next Page R/W 1 = Next page ability is enabled 0 = Next page ability is disabled 0 14 Reserved RO Ignore when read 13 Remote Fault R/W 1 = Transmit remote fault 0 12:11 Reserved RO Ignore when read 00 10 Pause R/W 1 = Pause operation for full-duplex 0 9 Advertise 100BASE-T4 RO 0 = Do not advertise T4 capability 0 8 Advertise 100BASE-TX FDX R/W 1 = Advertise 100BASE-TX full-duplex 0 = Do not advertise 100BASE-TX full-duplex 1 7 Advertise 100BASE-TX R/W 1 = Advertise 100BASE-TX 1 6 Advertise 10BASE-T FDX R/W 1 = Advertise 10BASE-T full-duplex 0 = Do not advertise 10BASE-T full-duplex 1 Note: R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL & LH Clear after read operation. Use default values of reserved bit(s) when writing to reserved bit(s). |
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