5222-DS02-R datasheet(20/76 Pages) BOARDCOM

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BCM5222

Preliminary Data Sheet

7/20/04

Broadcom Corporation

Page 8

Hardware Signal Definitions

Document 5222-DS02-405-R

F100

IPU

Force 100BASE-TX Control. When F100 is high and ANEN

is low, the transceiver is forced to 100BASE-TX operation.

When F100 is low and ANEN is low, the transceiver is forced

to 10BASE-T operation. When ANEN is high, F100 has no

effect on operation.

ANEN

IPU

Auto-Negotiation Enable. ANEN is active high. When pulled

high, auto-negotiation begins immediately after reset. When

low, auto-negotiation is disabled by default.

TESTEN

IPD

Test Mode Enable. Active high. Can float or be grounded for

normal operation.

J7,

53,

ADV_PAUSE{2},

ADV_PAUSE{1}

IPU

ADV_PAUSE. Active low. During power-on reset, this pin is

sampled and causes the default value of MII auto-negotiation

Advertisement register, 4, bit 10d to be set accordingly.

J10

MDIX_DIS

IPD

HP Auto-MDIX Disable. Active high. During power-on reset

if this pin is high the BCM5222 disables MDI cable cross-over

detection on both ports.

INTR

O3S

Interrupt. When the interrupt mode is enabled, pin becomes

INTR. This pin is shared by both PHY 1 and PHY 2.

K10

DLLTEST

IPU

DLL Test. This pin must be left unconnected during normal

operation.

BIAS

RDAC

DAC Bias Resistor. Adjusts the current level of the transmit

DAC. A resistor of 1.31 k

Ω±1% must be connected between

the RDAC pin and GND.

LEDS

F5, G9

18, 60

LNKLED{2}, LNKLED{1}

O3S

Link Integrity LED. The Link Integrity LED indicates the link

status of the PHY. LNKLED is driven low when the link to the

PHY is good.

F2, G7

20, 58

SPDLED{2}, SPDLED{1}

O3S

100BASE-TX LED. The 100 Base-TX LED is driven low when

operating in 100BASE-TX modes and high when operating in

10BASE-T modes.

F3, G6

21, 57

FDXLED{2}, FDXLED{1}

O3S

Full-Duplex LED. Driven low when the link is full-duplex and

driven high in half-duplex.

F4, G10

19, 59

ACTLED{2}, ACTLED{1}

O3S

Activity LED. Active low output. The receive activity LED is

driven low for approximately 80 ms each time there is receive

or transmit activity, while in the link pass state.

JTAG

TRST

IPD

Test Reset. Must be set low for normal operation, holding the

JTAG circuitry in reset. Transition from low to high initializes

the JTAG Tap Controller to the test-logic-reset state. Hold

high during JTAG.

TCK/FDX

IPU

Test Clock. This pin becomes TCK if TRST pin is high. Clock

input used to synchronize JTAG TAP control and data

transfers.

TDI/TXER{2}

IPD

Test Data Input. This pin becomes TDI if TRST is high. Data

or instruction input for JTAG test logic. Sampled on the rising

edge of TCK.

Table 3: Pin Descriptions (Cont.)

BGA

MQFP

Pin Label

Type

Description

[MSB:LSB]; OVERLINE = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD

= open-drain output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground

5222-DS02-R 数据表(PDF) 20 Page - Broadcom Corporation.

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