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MC56F81663 数据表(PDF) 23 Page - NXP Semiconductors |
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MC56F81663 数据表(HTML) 23 Page - NXP Semiconductors |
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23 / 73 page ![]() Table 2. Signal descriptions (continued) Signal Name 64 LQFP 48 LQFP 32 LQFP/ QFN State During Reset Type Signal Description XB_OUT6 Output Crossbar module output 6. GPIOE3 48 36 24 Input Input/ Output GPIO Port E3 — After reset, the default state is GPIOE3. (PWMA_1A) Input/ Output PWM submodule 1, high resolution output A or input capture A. (XB_OUT7) Output Crossbar module output 7. GPIOE4 51 39 25 Input Input/ Output GPIO Port E4 — After reset, the default state is GPIOE4. (PWMA_2B) Input/ Output PWM submodule 2, high resolution output B or input capture B. (XB_IN2) Input Crossbar module input 2 (LP_SCL1) Input/ Open- drain Output I2C1 serial clock line NOTE: In 4-wire mode, this is the I2C slave SCL input. (XB_OUT8) Output Crossbar module output 8. GPIOE5 52 40 26 Input Input/ Output GPIO Port E5 — After reset, the default state is GPIOE5. (PWMA_2A) Input/ Output PWM submodule 2, high resolution output A or input capture A (XB_IN3) Input Crossbar module input 3. (LP_SDA1) Input/ Open- drain Output I2C1 serial data line NOTE: In 4-wire mode, this is the I2C slave SDA input. (XB_OUT9) Output Crossbar module output 9. GPIOE6 53 — — Input Input/ Output GPIO Port E6 — After reset, the default state is GPIOE6. (PWMA_3B) Input/ Output PWM submodule 3, high resolution output B or input capture B. (XB_IN4) Input Crossbar module input 4 (XB_OUT10) Output Crossbar module output 10. GPIOE7 54 — — Input Input/ Output GPIO Port E7 — After reset, the default state is GPIOE7. (PWMA_3A) Input/ Output PWM ,submodule 3, high resolution output A or input capture A. (XB_IN5) Input Crossbar module input 5. (XB_OUT11) Output Crossbar module output 11. GPIOF0 36 28 — Input Input/ Output GPIO Port F0 — After reset, the default state is GPIOF0. (XB_IN6) Input Crossbar module input 6 (OPAMPB_OUT) Output Operational amplifier B output. Table continues on the next page... MC56F81xxx signal and pin descriptions MC56F81xxx, Rev. 1.1, 12/2020 NXP Semiconductors 23 |
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