MC56F81663 datasheet(12/73 Pages) NXP

12 / 73 page

1.5.15 Power supervisor

• Power-on reset (POR) is released after VDD > 2.7 V during supply is ramped up;

CPU, peripherals, and JTAG/EOnCE controllers exit RESET state

• Brownout reset (VDD < 2.0 V)

• Critical warn low-voltage interrupt (LVI 2.2 V)

• Peripheral low-voltage warning interrupt (LVI 2.7 V)

1.5.16 Phase-locked loop

• Output frequency range is optimized from 200 MHz to 550 MHz

• Input reference clock frequency: 8 MHz to 16 MHz

• Detection of loss of lock and loss of reference clock

• Ability to power down

Clock sources

1.5.17.1 On-chip oscillators

• Tunable 8 MHz RC oscillator with 2 MHz at standby mode

• 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT

1.5.17.2 Crystal oscillator

• Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic

resonator

• Operating frequency: 4–16 MHz

1.5.18 Cyclic Redundancy Check (CRC) generator

• Hardware 16/32-bit CRC generator

• High-speed hardware CRC calculation

• Programmable initial seed value

• Programmable 16/32-bit polynomial

• Error detection for all single, double, odd, and most multi-bit errors

• Option to transpose input data or output data (CRC result) bitwise or bytewise,1

which is required for certain CRC standards

• Option for inversion of final CRC result

1.5.17

1. A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user

software must perform the bytewise transposition.

Clock sources

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 数据表(PDF) 12 Page - NXP Semiconductors