MC56F81663 datasheet(6/73 Pages) NXP

6 / 73 page

• Dedicated time-base counter with period and frequency control per submodule

• Independent top and bottom deadtime insertion for each complementary pair

• Independent control of both edges of each PWM output

• Enhanced input capture and output compare functionality on each input:

• Channels not used for PWM generation can be used for buffered output compare

functions.

• Channels not used for PWM generation can be used for input capture functions.

• Enhanced dual edge capture functionality

• Synchronization of submodule to external hardware (or other PWM) is supported.

• Double-buffered PWM registers

• Integral reload rates from 1 to 16

• Half-cycle reload capability

• Multiple output trigger events can be generated per PWM cycle via hardware.

• Support for double-switching PWM outputs

• Up to eight fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Individual software control of each PWM output

• All outputs can be programmed to change simultaneously via a FORCE_OUT event.

• PWMX pin can optionally output a third PWM signal from each submodule

• Option to supply the source for each complementary PWM signal pair from any of

the following:

• Crossbar module outputs

• External ADC input, taking into account values set in ADC high and low limit

registers

• 312 ps resolution can be enabled for period, duty and deadtime related registers

• Direct phase shift controls among each submodule

• Trigger signal can share the same load frequency as reload signal in each submodule

1.5.2 12-bit Analog-to-Digital Converter (Cyclic type)

• Two independent 12-bit analog-to-digital converters (ADCs):

• 2 x 8-channel external inputs

• Built-in x1, x2, x4 programmable gain pre-amplifier

• Maximum ADC clock frequency up to 12.5 MHz, having period as low as 80 ns

• Single conversion time of 10 ADC clock cycles

• Additional conversion time of 8 ADC clock cycles

• Support of analog inputs for single-ended and differential (including unipolar

differential) conversions

• Sequential and parallel scan modes. Parallel mode includes simultaneous and

independent scan modes.

Peripheral highlights

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 数据表(PDF) 6 Page - NXP Semiconductors

MC56F81663 数据表(HTML) 6 Page - NXP Semiconductors

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