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MC56F81663 数据表(PDF) 51 Page - NXP Semiconductors |
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MC56F81663 数据表(HTML) 51 Page - NXP Semiconductors |
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51 / 73 page  Table 20. External clock operation timing requirements (continued) Characteristic Symbol Min Typ Max Unit Input high voltage overdrive by an external clock Vih 0.85×VDD — — V Input low voltage overdrive by an external clock Vil — — 0.3×VDD V 1. See the "External clock timing" figure for details on using the recommended connection of an external clock driver. 2. The chip may not function if the high or low pulse width is smaller than 6.25 ns. 3. External clock input rise time is measured from 10% to 90%. 4. External clock input fall time is measured from 90% to 10%. 90% 50% 10% 90% 50% 10% External Clock tPW tPW tfall trise VIL VIH Note: The midpoint is VIL + (VIH – VIL)/2. Figure 9. External clock timing 11.3.2 Phase-Locked Loop timing Table 21. Phase-Locked Loop timing Characteristic Symbol Min Typ Max Unit PLL input reference frequency1 fref 8 8 16 MHz PLL output frequency2 fop 200 — 550 MHz PLL lock time3 tplls — — 100 µs Allowed Duty Cycle of input reference tdc 40 50 60 % 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8 MHz input. 2. The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to 400 MHz. 3. This is the time required after the PLL is enabled to ensure reliable operation. 11.3.3 External crystal or resonator requirement Table 22. Crystal or resonator requirement Characteristic Symbol Min Typ Max Unit Frequency of operation fXOSC 4 8 16 MHz System modules MC56F81xxx, Rev. 1.1, 12/2020 NXP Semiconductors 51 |
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