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MC56F81663 数据表(PDF) 49 Page - NXP Semiconductors

部件名 MC56F81663
功能描述  DSC based on 32-bit 56800EX core
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MC56F81663 数据表(HTML) 49 Page - NXP Semiconductors

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Peripheral operating requirements and behaviors
11.1 Core modules
11.1.1 JTAG timing
Table 17. JTAG timing
Characteristic
Symbol
Min
Max
Unit
See
Figure
TCK frequency of operation
fOP
DC
SYS_CLK/ 8
MHz
Figure 7
TCK clock pulse width
tPW
50
—
ns
Figure 7
TMS, TDI data set-up time
tDS
5
—
ns
Figure 8
TMS, TDI data hold time
tDH
5
—
ns
Figure 8
TCK low to TDO data valid
tDV
—
30
ns
Figure 8
TCK low to TDO tri-state
tTS
—
30
ns
Figure 8
TCK
(Input)
VM
VIL
VM = VIL + (VIH – VIL)/2
tPW
1/fOP
tPW
VM
VIH
Figure 7. Test clock input timing diagram
Input Data Valid
Output Data Valid
tDS
tDH
tDV
tTS
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TMS
Figure 8. Test access port timing diagram
11
Peripheral operating requirements and behaviors
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
49



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