MC56F81663 datasheet(69/73 Pages) NXP

69 / 73 page

The thermal characterization parameter is measured per JESD51–2 specification using a

40-gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over

about 1 mm of wire extending from the junction. The thermocouple wire is placed flat

against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

To determine the junction temperature of the device in the application when heat

sinks are used, the junction temperature is determined from a thermocouple inserted at

the interface between the case of the package and the interface material. A clearance slot

or hole is normally required in the heat sink. Minimizing the size of the clearance is

important to minimize the change in thermal performance caused by removing part of the

thermal interface to the heat sink. Because of the experimental difficulties with this

technique, many engineers measure the heat sink temperature and then back-calculate the

case temperature using a separate measurement of the thermal resistance of the interface.

From this case temperature, the junction temperature is determined from the junction-to-

case thermal resistance.

12.2 Electrical design considerations

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields. However,

take normal precautions to avoid application of any voltages

higher than maximum-rated voltages to this high-impedance

circuit. Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the device:

• Provide a low-impedance path from the board power supply to each VDD pin on the

device and from the board ground to each VSS (GND) pin.

• The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as

near as possible to the package supply pins. The recommended bypass configuration

is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA.

Ceramic and tantalum capacitors tend to provide better tolerances.

• Ensure that capacitor leads and associated printed circuit traces that connect to the

chip VDD and VSS (GND) pins are as short as possible.

• Bypass the VDD and VSS with approximately 100 µF, plus the number of 0.1 µF

ceramic capacitors.

• PCB trace lengths should be minimal for high-frequency signals.

Design Considerations

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 数据表(PDF) 69 Page - NXP Semiconductors

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