MC56F81663 datasheet(61/73 Pages) NXP

61 / 73 page

PWMs and timers

11.6.1 Enhanced NanoEdge PWM characteristics

Table 32. NanoEdge PWM timing parameters

Characteristic

Symbol

Min

Typ

Max

Unit

PWM clock frequency

100

MHz

NanoEdge Placement (NEP) Step Size1, 2

pwmp

312

Delay for fault input activating to PWM output deactivated

Power-up Time3

tpu

µs

Resolution of Deadtime

312

1. Reference IPbus clock of 100 MHz in NanoEdge Placement mode.

2. Temperature and voltage variations do not affect NanoEdge Placement step size.

3. Powerdown to NanoEdge mode transition.

11.6.2 Quad Timer timing

Parameters listed are guaranteed by design.

Table 33. Timer timing

Characteristic

Symbol

Min1

Max

Unit

See Figure

Timer input period

2T + 6

—

Figure 14

Timer input high/low period

PINHL

1T + 3

—

Figure 14

Timer output period

POUT

—

Figure 14

Timer output high/low period

POUTHL

—

Figure 14

1. T = clock cycle. For 100 MHz operation, T = 10 ns.

POUT

POUTHL

PINHL

Timer Inputs

Timer Outputs

Figure 14. Timer timing

11.6

PWMs and timers

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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