MC56F81663 datasheet(48/73 Pages) NXP

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10.5.1 Thermal operating requirements

Table 16. Thermal operating requirements

Symbol

Description

Grade

Min

Max

Unit

Die junction temperature

–40

125

°C

–40

135

°C

Ambient temperature

–40

105

°C

–40

125

°C

10.5.2 Thermal attributes

This section provides information about operating temperature range, power dissipation,

and package thermal resistance. Power dissipation on I/O pins is usually small compared

to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-

determined rather than being controlled by the MCU design. To account for PI/O in power

calculations, determine the difference between actual pin voltage and VSS or VDD and

multiply by the pin current for each I/O pin. Except in cases of unusually high pin current

(heavy loads), the difference between pin voltage and VSS or VDD is very small.

See Thermal design considerations for more detail on thermal design considerations.

Board type 1

Symbol

Description

48 LQFP

64 LQFP

Unit

Notes

Four-layer

(2s2p)

RθJA

Thermal

resistance,

junction to

ambient (natural

convection)

°C/W

Single-layer

(1s)

RθJC

Thermal

resistance,

junction to case

°C/W

—

ΨJT

Thermal

characterization

parameter,

junction to

package top

outside center

(natural

convection)

°C/W

1. Thermal test board meets JEDEC specification for this package (JESD51-7, 2s2p and JESD51-3, 1s).

2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is

solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not

meant to predict the performance of a package in an application-specific environment.

3. Junction-to-Case (Top) thermal resistance is determined using an isothermal cold plate attached to the package top. Case

(Top) temperature refers to the mold surface temperature at the center.

General

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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